Hi all, As you may have seen, we have posted a number of patches that improve the fidelity of the classic interconnect models, along with quite some fixes for the caches and CPUs. Unsurprisingly these patches shake up the regression stats quite a bit, and I encourage anyone interested in memory-system performance to have a look and provide feedback. I hope to push these patches next week.
Thanks, Andreas # Port flow control http://reviews.gem5.org/r/2646/ (already got Ship It) # ARM CPU timings and TLB organisation http://reviews.gem5.org/r/2647/ http://reviews.gem5.org/r/2658/ # Device fixes http://reviews.gem5.org/r/2659/ # Crossbar timings http://reviews.gem5.org/r/2660/ http://reviews.gem5.org/r/2661/ http://reviews.gem5.org/r/2662/ # Cache fixes http://reviews.gem5.org/r/2663/ http://reviews.gem5.org/r/2664/ http://reviews.gem5.org/r/2670/ -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
