-- EDIT : erf sorry I messed up the object Hi everyone, I'd like to submit another problem to the community !
My setup now is a CPU (a TrafficGen CPU instance) that send memory request to a L1 Cache . All the Memory system is simulated with Ruby. I'd like to simulate several data caches for the same level of hierarchy, like one cache for some data and one cache for some others data, the caches do not handle the same memory accesses and the CPU decide which cache to access. I don't know if some examples are already available somewhere. So far, I tried to add an other controller + sequencer + cache to the CPU and to connect it to a second Master port of the cpu. Is it the right way to do it ? The config.ini file seems ok, I mean everything seems to be connected well, but i have a strange segfault If someone have already done that before ! -- Grégory Vaumourin Doctorant - Phd Student Laboratoire Adéquation Algorithme Architecture -- Matching Algorithm Architecture Laboratory Phone: +33 (1) 69080069 _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
