Hi Grégory, You may want to look at the L1 caches of protocols like MOESI_hammer that have separate instruction and data caches. Basically, what you need to do is add a new CacheMemory object to the Ruby Controller for every type of data that you want to cache. Then you'll need to modify the protocol to be aware of all of those different caches. You'll probably have to modify the messages, L1 machine, and possibly the CPU model to pass on the information that is important to your technique.
Externally, the Ruby cache hierarchy looks like one big crossbar with inputs from the CPUs and outputs to memory. Internally, there's structure provided via the Ruby topology which routes messages to their respective controllers. Each controller is defined in a .sm file in src/mem/protocols/ and the controllers explicitly specify the destination for all of the messages they send. Overall, setting up Ruby to have several data caches as you describe is much more complicated than just hooking up ports. Hopefully this will help you head in the right direction. Cheers, Jason On Tue Feb 24 2015 at 10:14:25 AM VAUMOURIN Grégory <[email protected]> wrote: > -- EDIT : erf sorry I messed up the object > > Hi everyone, I'd like to submit another problem to the community ! > > My setup now is a CPU (a TrafficGen CPU instance) that send memory request > to a L1 Cache . All the Memory system is simulated with Ruby. > I'd like to simulate several data caches for the same level of hierarchy, > like one cache for some data and one cache for some others data, the caches > do not handle the same memory accesses and the CPU decide which cache to > access. I don't know if some examples are already available somewhere. > > So far, I tried to add an other controller + sequencer + cache to the CPU > and to connect it to a second Master port of the cpu. Is it the right way > to do it ? > The config.ini file seems ok, I mean everything seems to be connected > well, but i have a strange segfault > If someone have already done that before ! > -- > Grégory Vaumourin > Doctorant - Phd Student > Laboratoire Adéquation Algorithme Architecture -- Matching Algorithm > Architecture Laboratory > Phone: +33 (1) 69080069 > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
