changeset ced453290507 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ced453290507
description:
cpu: o3 register renaming request handling improved
Now, prior to the renaming, the instruction requests the exact amount of
registers it will need, and the rename_map decides whether the
instruction is
allowed to proceed or not.
diffstat:
src/cpu/base_dyn_inst.hh | 1 +
src/cpu/o3/rename_impl.hh | 6 ++++--
src/cpu/o3/rename_map.hh | 23 +++++++++++++++++++++++
src/cpu/static_inst.hh | 3 +++
4 files changed, 31 insertions(+), 2 deletions(-)
diffs (83 lines):
diff -r 9ba5e70964a4 -r ced453290507 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Mon Mar 02 04:00:37 2015 -0500
+++ b/src/cpu/base_dyn_inst.hh Mon Mar 02 04:00:38 2015 -0500
@@ -594,6 +594,7 @@
// for machines with separate int & FP reg files
int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
+ int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
/** Returns the logical register index of the i'th destination register. */
RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
diff -r 9ba5e70964a4 -r ced453290507 src/cpu/o3/rename_impl.hh
--- a/src/cpu/o3/rename_impl.hh Mon Mar 02 04:00:37 2015 -0500
+++ b/src/cpu/o3/rename_impl.hh Mon Mar 02 04:00:38 2015 -0500
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012, 2014 ARM Limited
+ * Copyright (c) 2010-2012, 2014-2015 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -633,7 +633,9 @@
// Check here to make sure there are enough destination registers
// to rename to. Otherwise block.
- if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
+ if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
+ inst->numFPDestRegs(),
+ inst->numCCDestRegs())) {
DPRINTF(Rename, "Blocking due to lack of free "
"physical registers to rename to.\n");
blockThisCycle = true;
diff -r 9ba5e70964a4 -r ced453290507 src/cpu/o3/rename_map.hh
--- a/src/cpu/o3/rename_map.hh Mon Mar 02 04:00:37 2015 -0500
+++ b/src/cpu/o3/rename_map.hh Mon Mar 02 04:00:38 2015 -0500
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -346,6 +358,17 @@
{
return std::min(intMap.numFreeEntries(), floatMap.numFreeEntries());
}
+
+ /**
+ * Return whether there are enough registers to serve the request.
+ */
+ bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t ccRegs) const
+ {
+ return intRegs <= intMap.numFreeEntries() &&
+ floatRegs <= floatMap.numFreeEntries() &&
+ ccRegs <= ccMap.numFreeEntries();
+ }
+
};
#endif //__CPU_O3_RENAME_MAP_HH__
diff -r 9ba5e70964a4 -r ced453290507 src/cpu/static_inst.hh
--- a/src/cpu/static_inst.hh Mon Mar 02 04:00:37 2015 -0500
+++ b/src/cpu/static_inst.hh Mon Mar 02 04:00:38 2015 -0500
@@ -117,6 +117,9 @@
/// Number of integer destination regs.
int8_t numIntDestRegs() const { return _numIntDestRegs; }
//@}
+ /// Number of coprocesor destination regs.
+ int8_t numCCDestRegs() const { return _numCCDestRegs; }
+ //@}
/// @name Flag accessors.
/// These functions are used to access the values of the various
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