changeset 235ff1c046df in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=235ff1c046df
description:
stats: updates due to recent changesets.
diffstat:
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 4 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
| 6 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
| 1150 ++--
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
| 2478 +++++-----
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
| 1064 ++--
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
| 1316 ++--
6 files changed, 3009 insertions(+), 3009 deletions(-)
diffs (truncated from 6633 to 300 lines):
diff -r a8a5eb637d72 -r 235ff1c046df
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
Fri Apr 03 11:42:10 2015 -0500
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
Fri Apr 03 11:42:11 2015 -0500
@@ -779,9 +779,9 @@
system.cpu0.iew.iewIQFullEvents 24728 #
Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 127466 #
Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 18891 #
Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 275684 #
Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect 275682 #
Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 374727
# Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 650411 #
Number of branch mispredicts detected at execute
+system.cpu0.iew.branchMispredicts 650409 #
Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 126563046 #
Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 22955767 #
Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 966765 #
Number of squashed instructions skipped in execute
diff -r a8a5eb637d72 -r 235ff1c046df
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
Fri Apr 03 11:42:10 2015 -0500
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
Fri Apr 03 11:42:11 2015 -0500
@@ -321,10 +321,10 @@
system.physmem_0.readEnergy 362653200 #
Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 256666320 #
Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 178852415040 #
Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 68967490005 #
Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy 68967548145 #
Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1611945575250 #
Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1860586561230 #
Total energy per rank (pJ)
-system.physmem_0.averagePower 667.497599 #
Core power per rank (mW)
+system.physmem_0.totalEnergy 1860586619370 #
Total energy per rank (pJ)
+system.physmem_0.averagePower 667.497600 #
Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2632498894488 #
Time in different power states
system.physmem_0.memoryStateTime::REF 91437840000 #
Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 #
Time in different power states
diff -r a8a5eb637d72 -r 235ff1c046df
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
Fri Apr 03 11:42:10 2015 -0500
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
Fri Apr 03 11:42:11 2015 -0500
@@ -1,135 +1,80 @@
---------- Begin Simulation Statistics ----------
+sim_seconds 51.111153 #
Number of seconds simulated
+sim_ticks 51111152682000
# Number of ticks simulated
final_tick 51111152682000
# Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
-host_inst_rate 904753 #
Simulator instruction rate (inst/s)
-host_mem_usage 665260 #
Number of bytes of host memory used
-host_op_rate 1063233 #
Simulator op (including micro ops) rate (op/s)
-host_seconds 1088.22 #
Real time elapsed on the host
-host_tick_rate 46967646801 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
+host_inst_rate 929959 #
Simulator instruction rate (inst/s)
+host_op_rate 1092854 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 48276126697 #
Simulator tick rate (ticks/s)
+host_mem_usage 712572 #
Number of bytes of host memory used
+host_seconds 1058.73 #
Real time elapsed on the host
sim_insts 984570519 #
Number of instructions simulated
sim_ops 1157031967 #
Number of ops (including micro ops) simulated
-sim_seconds 51.111153 #
Number of seconds simulated
-sim_ticks 51111152682000
# Number of ticks simulated
+system.voltage_domain.voltage 1 #
Voltage in Volts
+system.clk_domain.clock 1000 #
Clock period in ticks
+system.physmem.bytes_read::cpu.dtb.walker 412352 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 376512 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 5562740 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 74833672 #
Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 441792 #
Number of bytes read from this memory
+system.physmem.bytes_read::total 81627068 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 5562740 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5562740 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 103042944 #
Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 20580 #
Number of bytes written to this memory
+system.physmem.bytes_written::total 103063524 #
Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 6443 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 5883 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 127325 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1169289 #
Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6903 #
Number of read requests responded to by this memory
+system.physmem.num_reads::total 1315843 #
Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1610046 #
Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 2573 #
Number of write requests responded to by this memory
+system.physmem.num_writes::total 1612619 #
Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 8068 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 7367 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 108836 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1464136 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8644 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1597050 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 108836 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 108836 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2016056 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 403 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2016459 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2016056 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 8068 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 7367 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 108836 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1464539 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8644 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3613509 #
Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst 96
# Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.data 36
# Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 132 #
Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 96
# Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 96
# Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 24 #
Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.data 5 #
Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 29 #
Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 2 #
Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu.data 1 #
Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 3 #
Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 2
# Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 2 #
Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 2 #
Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.data 1 #
Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 3 #
Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages 122 #
Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 #
Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_full_pages 122 #
Number of full page size DMA reads (not PRD).
system.cf0.dma_read_txs 122 #
Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 #
Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 #
Number of bytes transfered via DMA writes.
-system.cf0.dma_write_full_pages 1666 #
Number of full page size DMA writes.
system.cf0.dma_write_txs 1669 #
Number of DMA write transactions.
-system.clk_domain.clock 1000 #
Clock period in ticks
-system.cpu.Branches 220088562 #
Number of branches fetched
-system.cpu.committedInsts 984570519 #
Number of instructions committed
-system.cpu.committedOps 1157031967 #
Number of ops (including micro ops) committed
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266
# number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 4564266
# number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545
# number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 4310545
# number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589
# miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589
# miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721
# number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 253721
# number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 177577339
# number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 177577339 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::cpu.data 171567259 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 171567259 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845
# miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.033845
# miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.data 6010080
# number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 6010080 #
number of ReadReq misses
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417
# number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 2008417
# number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_hits::cpu.data 424020
# number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 424020 #
number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879
# miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879
# miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397
# number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 1584397 #
number of SoftPFReq misses
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465
# number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 4562465
# number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464
# number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 4562464
# number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000
# miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000
# miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 1
# number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 1
# number of StoreCondReq misses
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583058
# number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total 1583058
# number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337709
# number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total 337709
# number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786673
# miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786673
# miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245349
# number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total 1245349
# number of WriteInvalidateReq misses
-system.cpu.dcache.WriteReq_accesses::cpu.data 162093127
# number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 162093127
# number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::cpu.data 159522870 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 159522870 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857
# miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.015857
# miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.data 2570257
# number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2570257 #
number of WriteReq misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
# average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan
# average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.data 339670466
# number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 339670466 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_hits::cpu.data 331090129 #
number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 331090129 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025261
# miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025261 #
miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.data 8580337 #
number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 8580337 #
number of demand (read+write) misses
-system.cpu.dcache.fast_writes 0 #
number of fast writes performed
-system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.data 341678883
# number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 341678883 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_hits::cpu.data 331514149 #
number of overall hits
-system.cpu.dcache.overall_hits::total 331514149 #
number of overall hits
-system.cpu.dcache.overall_miss_rate::cpu.data 0.029749
# miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.029749
# miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.data 10164734
# number of overall misses
-system.cpu.dcache.overall_misses::total 10164734 #
number of overall misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 198
# Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 299
# Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 15
# Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs 29.345233 #
Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses 1421167352 #
Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719
# Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999999
# Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999999 #
Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512
# Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1
# Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements 11612141 #
number of replacements
-system.cpu.dcache.tags.sampled_refs 11612653 #
Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses 1421167352 #
Number of tag accesses
-system.cpu.dcache.tags.tagsinuse 511.999719 #
Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 340776008 #
Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 33050500 #
Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks 8921315 #
number of writebacks
-system.cpu.dcache.writebacks::total 8921315 #
number of writebacks
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0
# DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
# Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
# Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
# Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
# Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
# Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
# Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
# Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 #
DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
# ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
# ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
# ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 #
DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
# Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
# Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
# DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
# DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
# DTB read misses
+system.cpu_clk_domain.clock 500 #
Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
# Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data
0 # Table walker requests started/completed,
data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst
0 # Table walker requests started/completed,
data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total
0 # Table walker requests started/completed,
data/inst
@@ -137,28 +82,35 @@
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst
0 # Table walker requests started/completed,
data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total
0 # Table walker requests started/completed,
data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
# Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
# Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
# DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
# ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
# ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
# DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
# DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
# DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
# DTB write misses
-system.cpu.dtb.accesses 352512518 #
DTB accesses
-system.cpu.dtb.align_faults 0 #
Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 82353 #
Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 11 #
Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 1139 #
Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 #
Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 49771 #
Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 352246803 #
DTB hits
-system.cpu.dtb.inst_accesses 0 #
ITB inst accesses
-system.cpu.dtb.inst_hits 0 #
ITB inst hits
-system.cpu.dtb.inst_misses 0 #
ITB inst misses
-system.cpu.dtb.misses 265715 #
DTB misses
-system.cpu.dtb.perms_faults 21651 #
Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 9303 #
Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 184208233 #
DTB read accesses
-system.cpu.dtb.read_hits 184014035 #
DTB read hits
-system.cpu.dtb.read_misses 194198 #
DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
# Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
# Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
# Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
# Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
# Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
# Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
# Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
# Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
# Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
# DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
# DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
# ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 #
DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 #
DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0
# DTB accesses
+system.cpu.dtb.walker.walks 265715 #
Table walker walks requested
+system.cpu.dtb.walker.walksLong 265715 #
Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walkWaitTime::samples 265715
# Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% #
Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 265715 #
Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walksPending::samples 22846000
# Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% #
Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 22846000 #
Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% #
Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% #
Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 228319
# Table walker page sizes translated
@@ -169,85 +121,28 @@
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
# Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319
# Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 494034
# Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkWaitTime::samples 265715
# Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% #
Table walker wait (enqueue to first request) latency
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