changeset 378b344385a8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=378b344385a8
description:
cpu: Remove the InOrderCPU from the tree
This patch takes the final step in removing the InOrderCPU from the
tree. Rest in peace.
The MinorCPU is now used to model an in-order microarchitecture, and
long term the MinorCPU will eventually be renamed InOrderCPU.
diffstat:
src/cpu/inorder/InOrderCPU.py | 77 -
src/cpu/inorder/InOrderTrace.py | 36 -
src/cpu/inorder/SConscript | 89 -
src/cpu/inorder/SConsopts | 33 -
src/cpu/inorder/comm.hh | 85 -
src/cpu/inorder/cpu.cc | 1922 ------------------------
src/cpu/inorder/cpu.hh | 942 -----------
src/cpu/inorder/first_stage.cc | 289 ---
src/cpu/inorder/first_stage.hh | 96 -
src/cpu/inorder/inorder_cpu_builder.cc | 61 -
src/cpu/inorder/inorder_dyn_inst.cc | 626 -------
src/cpu/inorder/inorder_dyn_inst.hh | 1090 -------------
src/cpu/inorder/inorder_trace.cc | 96 -
src/cpu/inorder/inorder_trace.hh | 98 -
src/cpu/inorder/pipeline_stage.cc | 1125 --------------
src/cpu/inorder/pipeline_stage.hh | 349 ----
src/cpu/inorder/pipeline_traits.5stage.cc | 166 --
src/cpu/inorder/pipeline_traits.5stage.hh | 145 -
src/cpu/inorder/pipeline_traits.9stage.cc | 242 ---
src/cpu/inorder/pipeline_traits.9stage.hh | 153 -
src/cpu/inorder/pipeline_traits.9stage.smt2.cc | 240 --
src/cpu/inorder/pipeline_traits.9stage.smt2.hh | 153 -
src/cpu/inorder/pipeline_traits.hh | 85 -
src/cpu/inorder/reg_dep_map.cc | 304 ---
src/cpu/inorder/reg_dep_map.hh | 115 -
src/cpu/inorder/resource.cc | 523 ------
src/cpu/inorder/resource.hh | 411 -----
src/cpu/inorder/resource_pool.9stage.cc | 361 ----
src/cpu/inorder/resource_pool.cc | 475 -----
src/cpu/inorder/resource_pool.hh | 250 ---
src/cpu/inorder/resource_sked.cc | 233 --
src/cpu/inorder/resource_sked.hh | 285 ---
src/cpu/inorder/resources/agen_unit.cc | 107 -
src/cpu/inorder/resources/agen_unit.hh | 64 -
src/cpu/inorder/resources/branch_predictor.cc | 181 --
src/cpu/inorder/resources/branch_predictor.hh | 87 -
src/cpu/inorder/resources/cache_unit.cc | 1297 ----------------
src/cpu/inorder/resources/cache_unit.hh | 269 ---
src/cpu/inorder/resources/decode_unit.cc | 97 -
src/cpu/inorder/resources/decode_unit.hh | 66 -
src/cpu/inorder/resources/execution_unit.cc | 249 ---
src/cpu/inorder/resources/execution_unit.hh | 83 -
src/cpu/inorder/resources/fetch_seq_unit.cc | 335 ----
src/cpu/inorder/resources/fetch_seq_unit.hh | 105 -
src/cpu/inorder/resources/fetch_unit.cc | 591 -------
src/cpu/inorder/resources/fetch_unit.hh | 139 -
src/cpu/inorder/resources/graduation_unit.cc | 135 -
src/cpu/inorder/resources/graduation_unit.hh | 67 -
src/cpu/inorder/resources/inst_buffer.cc | 241 ---
src/cpu/inorder/resources/inst_buffer.hh | 93 -
src/cpu/inorder/resources/mem_dep_unit.hh | 66 -
src/cpu/inorder/resources/mult_div_unit.cc | 353 ----
src/cpu/inorder/resources/mult_div_unit.hh | 139 -
src/cpu/inorder/resources/resource_list.hh | 50 -
src/cpu/inorder/resources/tlb_unit.cc | 259 ---
src/cpu/inorder/resources/tlb_unit.hh | 152 -
src/cpu/inorder/resources/use_def.cc | 510 ------
src/cpu/inorder/resources/use_def.hh | 135 -
src/cpu/inorder/thread_context.cc | 314 ---
src/cpu/inorder/thread_context.hh | 317 ---
src/cpu/inorder/thread_state.cc | 44 -
src/cpu/inorder/thread_state.hh | 103 -
62 files changed, 0 insertions(+), 17803 deletions(-)
diffs (truncated from 18051 to 300 lines):
diff -r e94c22bd9ef1 -r 378b344385a8 src/cpu/inorder/InOrderCPU.py
--- a/src/cpu/inorder/InOrderCPU.py Mon Apr 20 12:46:29 2015 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-# Copyright (c) 2007 MIPS Technologies, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Korey Sewell
-
-from m5.params import *
-from m5.proxy import *
-from BaseCPU import BaseCPU
-from BranchPredictor import *
-
-class ThreadModel(Enum):
- vals = ['Single', 'SMT', 'SwitchOnCacheMiss']
-
-class InOrderCPU(BaseCPU):
- type = 'InOrderCPU'
- cxx_header = "cpu/inorder/cpu.hh"
- activity = Param.Unsigned(0, "Initial count")
-
- @classmethod
- def memory_mode(cls):
- return 'timing'
-
- @classmethod
- def require_caches(cls):
- return True
-
- @classmethod
- def support_take_over(cls):
- return True
-
- threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE
only)")
-
- cachePorts = Param.Unsigned(2, "Cache Ports")
- stageWidth = Param.Unsigned(4, "Stage width")
-
- fetchBuffSize = Param.Unsigned(4, "Fetch Buffer Size (Number of Cache
Blocks Stored)")
- memBlockSize = Param.Unsigned(64, "Memory Block Size")
-
- stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU")
-
- multLatency = Param.Cycles(1, "Latency for Multiply Operations")
- multRepeatRate = Param.Cycles(1, "Repeat Rate for Multiply Operations")
- div8Latency = Param.Cycles(1, "Latency for 8-bit Divide Operations")
- div8RepeatRate = Param.Cycles(1, "Repeat Rate for 8-bit Divide Operations")
- div16Latency = Param.Cycles(1, "Latency for 16-bit Divide Operations")
- div16RepeatRate = Param.Cycles(1, "Repeat Rate for 16-bit Divide
Operations")
- div24Latency = Param.Cycles(1, "Latency for 24-bit Divide Operations")
- div24RepeatRate = Param.Cycles(1, "Repeat Rate for 24-bit Divide
Operations")
- div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations")
- div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide
Operations")
-
- branchPred = Param.BranchPredictor(TournamentBP(numThreads =
- Parent.numThreads),
- "Branch Predictor")
diff -r e94c22bd9ef1 -r 378b344385a8 src/cpu/inorder/InOrderTrace.py
--- a/src/cpu/inorder/InOrderTrace.py Mon Apr 20 12:46:29 2015 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,36 +0,0 @@
-# Copyright (c) 2007 MIPS Technologies, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Korey Sewell
-
-from m5.SimObject import SimObject
-from m5.params import *
-from InstTracer import InstTracer
-
-class InOrderTrace(InstTracer):
- type = 'InOrderTrace'
- cxx_class = 'Trace::InOrderTrace'
- cxx_header = "cpu/inorder/inorder_trace.hh"
diff -r e94c22bd9ef1 -r 378b344385a8 src/cpu/inorder/SConscript
--- a/src/cpu/inorder/SConscript Mon Apr 20 12:46:29 2015 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,89 +0,0 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2007 MIPS Technologies, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Korey Sewell
-
-Import('*')
-
-if 'InOrderCPU' in env['CPU_MODELS']:
- SimObject('InOrderCPU.py')
- SimObject('InOrderTrace.py')
-
- DebugFlag('ResReqCount')
- DebugFlag('InOrderStage')
- DebugFlag('InOrderStall')
- DebugFlag('InOrderCPU')
- DebugFlag('RegDepMap')
- DebugFlag('InOrderDynInst')
- DebugFlag('Resource')
- DebugFlag('InOrderAGEN')
- DebugFlag('InOrderFetchSeq')
- DebugFlag('InOrderTLB')
- DebugFlag('InOrderCachePort')
- DebugFlag('InOrderBPred')
- DebugFlag('InOrderDecode')
- DebugFlag('InOrderExecute')
- DebugFlag('InOrderInstBuffer')
- DebugFlag('InOrderUseDef')
- DebugFlag('InOrderMDU')
- DebugFlag('InOrderGraduation')
- DebugFlag('ThreadModel')
- DebugFlag('RefCount')
- DebugFlag('AddrDep')
- DebugFlag('SkedCache')
-
- CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall',
'InOrderCPU',
- 'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB',
'InOrderBPred',
- 'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer',
'InOrderUseDef',
- 'InOrderGraduation', 'InOrderCachePort', 'RegDepMap',
'Resource',
- 'InOrderStall','ThreadModel', 'AddrDep'])
-
- Source('inorder_dyn_inst.cc')
- Source('inorder_cpu_builder.cc')
- Source('inorder_trace.cc')
- Source('pipeline_stage.cc')
- Source('first_stage.cc')
- Source('resource.cc')
- Source('resources/agen_unit.cc')
- Source('resources/execution_unit.cc')
- Source('resources/branch_predictor.cc')
- Source('resources/cache_unit.cc')
- Source('resources/fetch_unit.cc')
- Source('resources/use_def.cc')
- Source('resources/decode_unit.cc')
- Source('resources/inst_buffer.cc')
- Source('resources/graduation_unit.cc')
- Source('resources/fetch_seq_unit.cc')
- Source('resources/mult_div_unit.cc')
- Source('resource_pool.cc')
- Source('resource_sked.cc')
- Source('reg_dep_map.cc')
- Source('thread_state.cc')
- Source('thread_context.cc')
- Source('cpu.cc')
-
diff -r e94c22bd9ef1 -r 378b344385a8 src/cpu/inorder/SConsopts
--- a/src/cpu/inorder/SConsopts Mon Apr 20 12:46:29 2015 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,33 +0,0 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2007 MIPS Technologies, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Korey Sewell
-
-Import('*')
-
-CpuModel('InOrderCPU', default=True)
diff -r e94c22bd9ef1 -r 378b344385a8 src/cpu/inorder/comm.hh
--- a/src/cpu/inorder/comm.hh Mon Apr 20 12:46:29 2015 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,85 +0,0 @@
-/*
- * Copyright (c) 2007 MIPS Technologies, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Korey Sewell
- *
- */
-
-#ifndef __CPU_INORDER_COMM_HH__
-#define __CPU_INORDER_COMM_HH__
-
-#include <vector>
-
-#include "arch/isa_traits.hh"
-#include "base/types.hh"
-#include "cpu/inorder/inorder_dyn_inst.hh"
-#include "cpu/inorder/pipeline_traits.hh"
-#include "cpu/inst_seq.hh"
-
-/** Struct that defines the information passed from in between stages */
-/** This information mainly goes forward through the pipeline. */
-struct InterStageStruct {
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