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Review request for Default. Repository: gem5 Description ------- Changeset 10790:978c397951b2 --------------------------- cpu: o3: single cycle default div microop latency on x86 This patch sets the default latency of the division microop to a single cycle on x86. This is because the division instructions DIV and IDIV have been implemented as loops of div microops, where each microop computes a single bit of the quotient. Diffs ----- src/cpu/o3/FuncUnitConfig.py d1df075f3b71 Diff: http://reviews.gem5.org/r/2744/diff/ Testing ------- Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
