On Mon, 27 Apr 2015, Brad Beckmann wrote:
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2749/#review6088
-----------------------------------------------------------
Responding to Nilay's comments over email:
I think it would be best if you explained the initial bug that led to
this patch.
I think the explanation in the original message is clear enough. The
coherence protocols expect there are multiple cpus when options.num_cpus >
1. Currently a single tester is created even when options.num_cpus > 1.
This is the bug.
Going forward, the tester will need to work with protocols that do not
expect simply a number of CPUs. There will be controllers that only
generate instruction fetches, and other controllers that support shared
i-caches and separate d-caches. In these protocols, understanding the
number of CPUs is not good enough. The tester will need to be more
flexible handling ports.
I don't follow what you want to say here. I think it would really good if
you post your patch and we then decide which code is better.
--
Nilay
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev