changeset 1e38e545823b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1e38e545823b
description:
arm: Add missing FPEXC.EN check
Add a missing check to ensure that exceptions are generated properly.
diffstat:
src/arch/arm/isa/insts/neon.isa | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diffs (43 lines):
diff -r 2e989cde3f2e -r 1e38e545823b src/arch/arm/isa/insts/neon.isa
--- a/src/arch/arm/isa/insts/neon.isa Tue May 05 03:22:42 2015 -0400
+++ b/src/arch/arm/isa/insts/neon.isa Tue May 05 03:22:45 2015 -0400
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010-2011 ARM Limited
+// Copyright (c) 2010-2011, 2015 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -3694,7 +3694,7 @@
def vdupGprInst(name, Name, opClass, types, rCount):
global header_output, exec_output
- eWalkCode = '''
+ eWalkCode = simdEnabledCheckCode + '''
RegVect destReg;
for (unsigned i = 0; i < eCount; i++) {
destReg.elements[i] = htog((Element)Op1);
@@ -3777,11 +3777,11 @@
def buildVext(name, Name, opClass, types, rCount, op):
global header_output, exec_output
- eWalkCode = '''
+ eWalkCode = simdEnabledCheckCode + '''
RegVect srcReg1, srcReg2, destReg;
'''
for reg in range(rCount):
- eWalkCode += simdEnabledCheckCode + '''
+ eWalkCode += '''
srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
''' % { "reg" : reg }
@@ -3825,7 +3825,7 @@
def buildVtbxl(name, Name, opClass, length, isVtbl):
global header_output, decoder_output, exec_output
- code = '''
+ code = simdEnabledCheckCode + '''
union
{
uint8_t bytes[32];
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