changeset 2e989cde3f2e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2e989cde3f2e
description:
arm: enable DCZVA by default in SE mode
diffstat:
src/arch/arm/miscregs.cc | 7 +++++--
1 files changed, 5 insertions(+), 2 deletions(-)
diffs (29 lines):
diff -r 7f5467f2f8b8 -r 2e989cde3f2e src/arch/arm/miscregs.cc
--- a/src/arch/arm/miscregs.cc Tue May 05 03:22:39 2015 -0400
+++ b/src/arch/arm/miscregs.cc Tue May 05 03:22:42 2015 -0400
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013 ARM Limited
+ * Copyright (c) 2010-2013, 2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -43,6 +43,7 @@
#include "arch/arm/miscregs.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
+#include "sim/full_system.hh"
namespace ArmISA
{
@@ -2138,7 +2139,9 @@
if (el == EL0 && !sctlr.uma)
return false;
}
- if (reg == MISCREG_DC_ZVA_Xt) {
+ if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
+ // In syscall-emulation mode, this test is skipped and DCZVA is always
+ // allowed at EL0
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
if (el == EL0 && !sctlr.dze)
return false;
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