changeset 169af9a2779f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=169af9a2779f
description:
mem: Remove templates in cache model
This patch changes the cache implementation to rely on virtual methods
rather than using the replacement policy as a template argument.
There is no impact on the simulation performance, and overall the
changes make it easier to modify (and subclass) the cache and/or
replacement policy.
diffstat:
src/mem/cache/base.cc | 16 +--
src/mem/cache/blk.hh | 60 +---------
src/mem/cache/cache.cc | 8 -
src/mem/cache/cache.hh | 106 ++++++++++++++----
src/mem/cache/cache_impl.hh | 190 ++++++++++++----------------------
src/mem/cache/tags/base.hh | 33 ++++++
src/mem/cache/tags/base_set_assoc.cc | 2 +-
src/mem/cache/tags/base_set_assoc.hh | 23 +---
src/mem/cache/tags/fa_lru.cc | 16 ++-
src/mem/cache/tags/fa_lru.hh | 33 ++---
src/mem/cache/tags/lru.cc | 10 +-
src/mem/cache/tags/lru.hh | 6 +-
src/mem/cache/tags/random_repl.cc | 10 +-
src/mem/cache/tags/random_repl.hh | 6 +-
14 files changed, 240 insertions(+), 279 deletions(-)
diffs (truncated from 1332 to 300 lines):
diff -r 46b6043bd32c -r 169af9a2779f src/mem/cache/base.cc
--- a/src/mem/cache/base.cc Tue May 05 03:22:19 2015 -0400
+++ b/src/mem/cache/base.cc Tue May 05 03:22:21 2015 -0400
@@ -783,21 +783,7 @@
BaseCache *
BaseCacheParams::create()
{
- unsigned numSets = size / (assoc * system->cacheLineSize());
-
assert(tags);
- if (dynamic_cast<FALRU*>(tags)) {
- if (numSets != 1)
- fatal("Got FALRU tags with more than one set\n");
- return new Cache<FALRU>(this);
- } else if (dynamic_cast<LRU*>(tags)) {
- if (numSets == 1)
- warn("Consider using FALRU tags for a fully associative cache\n");
- return new Cache<LRU>(this);
- } else if (dynamic_cast<RandomRepl*>(tags)) {
- return new Cache<RandomRepl>(this);
- } else {
- fatal("No suitable tags selected\n");
- }
+ return new Cache(this);
}
diff -r 46b6043bd32c -r 169af9a2779f src/mem/cache/blk.hh
--- a/src/mem/cache/blk.hh Tue May 05 03:22:19 2015 -0400
+++ b/src/mem/cache/blk.hh Tue May 05 03:22:21 2015 -0400
@@ -397,63 +397,19 @@
};
/**
- * Wrap a method and present it as a cache block visitor.
- *
- * For example the forEachBlk method in the tag arrays expects a
- * callable object/function as their parameter. This class wraps a
- * method in an object and presents callable object that adheres to
- * the cache block visitor protocol.
+ * Base class for cache block visitor, operating on the cache block
+ * base class (later subclassed for the various tag classes). This
+ * visitor class is used as part of the forEachBlk interface in the
+ * tag classes.
*/
-template <typename T, typename BlkType>
-class CacheBlkVisitorWrapper
+class CacheBlkVisitor
{
public:
- typedef bool (T::*visitorPtr)(BlkType &blk);
- CacheBlkVisitorWrapper(T &_obj, visitorPtr _visitor)
- : obj(_obj), visitor(_visitor) {}
+ CacheBlkVisitor() {}
+ virtual ~CacheBlkVisitor() {}
- bool operator()(BlkType &blk) {
- return (obj.*visitor)(blk);
- }
-
- private:
- T &obj;
- visitorPtr visitor;
-};
-
-/**
- * Cache block visitor that determines if there are dirty blocks in a
- * cache.
- *
- * Use with the forEachBlk method in the tag array to determine if the
- * array contains dirty blocks.
- */
-template <typename BlkType>
-class CacheBlkIsDirtyVisitor
-{
- public:
- CacheBlkIsDirtyVisitor()
- : _isDirty(false) {}
-
- bool operator()(BlkType &blk) {
- if (blk.isDirty()) {
- _isDirty = true;
- return false;
- } else {
- return true;
- }
- }
-
- /**
- * Does the array contain a dirty line?
- *
- * \return true if yes, false otherwise.
- */
- bool isDirty() const { return _isDirty; };
-
- private:
- bool _isDirty;
+ virtual bool operator()(CacheBlk &blk) = 0;
};
#endif //__CACHE_BLK_HH__
diff -r 46b6043bd32c -r 169af9a2779f src/mem/cache/cache.cc
--- a/src/mem/cache/cache.cc Tue May 05 03:22:19 2015 -0400
+++ b/src/mem/cache/cache.cc Tue May 05 03:22:21 2015 -0400
@@ -41,11 +41,3 @@
#include "mem/cache/tags/random_repl.hh"
#include "mem/cache/cache_impl.hh"
-// Template Instantiations
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template class Cache<FALRU>;
-template class Cache<LRU>;
-template class Cache<RandomRepl>;
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
diff -r 46b6043bd32c -r 169af9a2779f src/mem/cache/cache.hh
--- a/src/mem/cache/cache.hh Tue May 05 03:22:19 2015 -0400
+++ b/src/mem/cache/cache.hh Tue May 05 03:22:21 2015 -0400
@@ -56,6 +56,7 @@
#include "mem/cache/base.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/mshr.hh"
+#include "mem/cache/tags/base.hh"
#include "sim/eventq.hh"
//Forward decleration
@@ -66,17 +67,14 @@
* supplying different template policies. TagStore handles all tag and data
* storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
*/
-template <class TagStore>
class Cache : public BaseCache
{
public:
- /** Define the type of cache block to use. */
- typedef typename TagStore::BlkType BlkType;
- /** A typedef for a list of BlkType pointers. */
- typedef typename TagStore::BlkList BlkList;
+
+ /** A typedef for a list of CacheBlk pointers. */
+ typedef std::list<CacheBlk*> BlkList;
protected:
- typedef CacheBlkVisitorWrapper<Cache<TagStore>, BlkType> WrappedBlkVisitor;
/**
* The CPU-side port extends the base cache slave port with access
@@ -87,7 +85,7 @@
private:
// a pointer to our specific cache implementation
- Cache<TagStore> *cache;
+ Cache *cache;
protected:
@@ -103,7 +101,7 @@
public:
- CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
+ CpuSidePort(const std::string &_name, Cache *_cache,
const std::string &_label);
};
@@ -119,12 +117,12 @@
protected:
- Cache<TagStore> &cache;
+ Cache &cache;
SnoopRespPacketQueue &snoopRespQueue;
public:
- CacheReqPacketQueue(Cache<TagStore> &cache, MasterPort &port,
+ CacheReqPacketQueue(Cache &cache, MasterPort &port,
SnoopRespPacketQueue &snoop_resp_queue,
const std::string &label) :
ReqPacketQueue(cache, port, label), cache(cache),
@@ -153,7 +151,7 @@
SnoopRespPacketQueue _snoopRespQueue;
// a pointer to our specific cache implementation
- Cache<TagStore> *cache;
+ Cache *cache;
protected:
@@ -167,18 +165,18 @@
public:
- MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
+ MemSidePort(const std::string &_name, Cache *_cache,
const std::string &_label);
};
/** Tag and data Storage */
- TagStore *tags;
+ BaseTags *tags;
/** Prefetcher */
BasePrefetcher *prefetcher;
/** Temporary cache block for occasional transitory use */
- BlkType *tempBlock;
+ CacheBlk *tempBlock;
/**
* This cache should allocate a block on a line-sized write miss.
@@ -210,13 +208,13 @@
* @param writebacks List for any writebacks that need to be performed.
* @return Boolean indicating whether the request was satisfied.
*/
- bool access(PacketPtr pkt, BlkType *&blk,
+ bool access(PacketPtr pkt, CacheBlk *&blk,
Cycles &lat, PacketList &writebacks);
/**
*Handle doing the Compare and Swap function for SPARC.
*/
- void cmpAndSwap(BlkType *blk, PacketPtr pkt);
+ void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
/**
* Find a block frame for new block at address addr targeting the
@@ -225,7 +223,7 @@
* list. Return free block frame. May return NULL if there are
* no replaceable blocks at the moment.
*/
- BlkType *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
+ CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
/**
* Populates a cache block and handles all outstanding requests for the
@@ -236,7 +234,7 @@
* @param writebacks List for any writebacks that need to be performed.
* @return Pointer to the new cache block.
*/
- BlkType *handleFill(PacketPtr pkt, BlkType *blk,
+ CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
PacketList &writebacks);
@@ -287,10 +285,10 @@
*/
void functionalAccess(PacketPtr pkt, bool fromCpuSide);
- void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
+ void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk,
bool deferred_response = false,
bool pending_downgrade = false);
- bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
+ bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk);
void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
bool already_copied, bool pending_inval);
@@ -300,7 +298,7 @@
* @param blk The cache block being snooped.
* @param new_state The new coherence state for the block.
*/
- void handleSnoop(PacketPtr ptk, BlkType *blk,
+ void handleSnoop(PacketPtr ptk, CacheBlk *blk,
bool is_timing, bool is_deferred, bool pending_inval);
/**
@@ -308,7 +306,7 @@
* @param blk The block to writeback.
* @return The writeback request for the block.
*/
- PacketPtr writebackBlk(BlkType *blk);
+ PacketPtr writebackBlk(CacheBlk *blk);
void memWriteback();
@@ -321,7 +319,7 @@
*
* \return Always returns true.
*/
- bool writebackVisitor(BlkType &blk);
+ bool writebackVisitor(CacheBlk &blk);
/**
* Cache block visitor that invalidates all blocks in the cache.
*
@@ -329,7 +327,7 @@
*
* \return Always returns true.
*/
- bool invalidateVisitor(BlkType &blk);
+ bool invalidateVisitor(CacheBlk &blk);
/**
* Squash all requests associated with specified thread.
@@ -349,7 +347,7 @@
* @return A new Packet containing the request, or NULL if the
* current request in cpu_pkt should just be forwarded on.
*/
- PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
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