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(Updated May 26, 2015, 12:44 p.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 10818:d8ed395159dc --------------------------- cpu: Add store-access operations This patch was created by Bihn Pham during his internship at AMD. This patch adds decoupled store operations that are commonly used by high-performance processors. The patch modifies the O3 CPU model to issue StoreAccess operations as soon as possible to acquire exclusive permission for eventual stores. Later data store operations behave as normal. In the classic memory model, StoreAccess requests are treated as HardPFExReq and share the existing prefetch queue. Therefore, they affect performance only if the prefetcher is enabled in the classic model. In Ruby, StoreAccess requests are treated as RubyStore with NULL data field. Diffs (updated) ----- src/cpu/o3/lsq_unit.hh df2aa91dba5b0f0baa351039f0802baad9ed8f1d src/cpu/o3/lsq_unit_impl.hh df2aa91dba5b0f0baa351039f0802baad9ed8f1d src/mem/abstract_mem.cc df2aa91dba5b0f0baa351039f0802baad9ed8f1d src/mem/cache/cache_impl.hh df2aa91dba5b0f0baa351039f0802baad9ed8f1d src/mem/cache/mshr.cc df2aa91dba5b0f0baa351039f0802baad9ed8f1d src/mem/cache/prefetch/queued.cc df2aa91dba5b0f0baa351039f0802baad9ed8f1d src/mem/packet.hh df2aa91dba5b0f0baa351039f0802baad9ed8f1d src/mem/packet.cc df2aa91dba5b0f0baa351039f0802baad9ed8f1d src/mem/protocol/RubySlicc_Exports.sm df2aa91dba5b0f0baa351039f0802baad9ed8f1d src/mem/ruby/system/RubyPort.hh df2aa91dba5b0f0baa351039f0802baad9ed8f1d src/mem/ruby/system/RubyPort.cc df2aa91dba5b0f0baa351039f0802baad9ed8f1d src/mem/ruby/system/Sequencer.cc df2aa91dba5b0f0baa351039f0802baad9ed8f1d Diff: http://reviews.gem5.org/r/2788/diff/ Testing ------- Thanks, Tony Gutierrez _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
