----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2852/ -----------------------------------------------------------
(Updated May 29, 2015, 9:06 p.m.) Review request for Default. Changes ------- Updating commit message. Repository: gem5 Description (updated) ------- Changeset 10860:f4565ce598dd --------------------------- x86, o3: Enabling x86 TLBs for multiple hardware threads This patch extends the x86 TLB to be shared among multiple hardware threads. Its size will represent the total number of TLB entries that can be allocated to all threads. Diffs ----- src/arch/x86/tlb.hh d02b45a554b52c68cce41e1b3895fb8582a639dd src/arch/x86/tlb.cc d02b45a554b52c68cce41e1b3895fb8582a639dd src/cpu/o3/cpu.cc d02b45a554b52c68cce41e1b3895fb8582a639dd src/arch/generic/tlb.hh d02b45a554b52c68cce41e1b3895fb8582a639dd src/arch/x86/isa.cc d02b45a554b52c68cce41e1b3895fb8582a639dd src/arch/x86/pagetable.hh d02b45a554b52c68cce41e1b3895fb8582a639dd src/arch/x86/pagetable.cc d02b45a554b52c68cce41e1b3895fb8582a639dd src/arch/x86/pagetable_walker.cc d02b45a554b52c68cce41e1b3895fb8582a639dd Diff: http://reviews.gem5.org/r/2852/diff/ Testing ------- Quick regressions passed for all ISAs. Thanks, Alexandru Dutu _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
