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(Updated June 27, 2015, 12:37 a.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 10882:521d9e4fd885 --------------------------- x86: reimplment SSE instructions using new vector registers This patch removes the old xmm registers and adds new vector registers to the x86 architecture. SIMD instructions using xmm registers have been reimplemented to use the new set of registers. Diffs (updated) ----- src/arch/x86/isa/microops/vector-ops.isa PRE-CREATION src/arch/x86/isa/operands.isa 73d4798871a5 src/arch/x86/memhelpers.hh 73d4798871a5 src/arch/x86/nativetrace.hh 73d4798871a5 src/arch/x86/nativetrace.cc 73d4798871a5 src/arch/x86/registers.hh 73d4798871a5 src/arch/x86/regs/float.hh 73d4798871a5 src/arch/x86/regs/vector.hh PRE-CREATION src/arch/x86/utility.hh 73d4798871a5 src/arch/x86/utility.cc 73d4798871a5 src/arch/x86/x86_traits.hh 73d4798871a5 src/cpu/kvm/x86_cpu.cc 73d4798871a5 src/cpu/o3/O3CPU.py 73d4798871a5 src/cpu/simple_thread.hh 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_integer_to_floating_point.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_mmx_integer_to_floating_point.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/data_reordering/extract_and_insert.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/data_reordering/pack_with_saturation.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/data_reordering/shuffle.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/data_reordering/unpack_and_interleave.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/data_transfer/move_mask.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/data_transfer/move_non_temporal.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/logical/exclusive_or.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/logical/pand.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/logical/por.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py 73d4798871a5 src/arch/x86/isa/microasm.isa 73d4798871a5 src/arch/x86/isa/microops/ldstop.isa 73d4798871a5 src/arch/x86/isa/microops/mediaop.isa 73d4798871a5 src/arch/x86/isa/microops/microops.isa 73d4798871a5 src/arch/x86/SConscript 73d4798871a5 src/arch/x86/insts/microvectorop.hh PRE-CREATION src/arch/x86/insts/microvectorop.cc PRE-CREATION src/arch/x86/insts/static_inst.hh 73d4798871a5 src/arch/x86/insts/static_inst.cc 73d4798871a5 src/arch/x86/isa/decoder/two_byte_opcodes.isa 73d4798871a5 src/arch/x86/isa/includes.isa 73d4798871a5 src/arch/x86/isa/insts/general_purpose/data_transfer/move.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/arithmetic/addition.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/arithmetic/division.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/arithmetic/simultaneous_addition_and_subtraction.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/arithmetic/square_root.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_mask.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_minimum_or_maximum.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_rflags.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_mmx_integer.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_xmm_integer.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/data_reordering/shuffle.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/data_reordering/unpack_and_interleave.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_mask.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_with_duplication.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/logical/andp.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/logical/exclusive_or.py 73d4798871a5 src/arch/x86/isa/insts/simd128/floating_point/logical/orp.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/arithmetic/addition.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/arithmetic/average.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/arithmetic/multiply_add.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/arithmetic/subtraction.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/arithmetic/sum_of_absolute_differences.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_mask.py 73d4798871a5 src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_minimum_or_maximum.py 73d4798871a5 Diff: http://reviews.gem5.org/r/2888/diff/ Testing ------- Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
