On Tue, 14 Jul 2015, David Hashe wrote:
On July 14, 2015, 3:01 p.m., Nilay Vaish wrote:
Are you assuming that physical memory size is a power of 2?
If the physical memory size is not a power of 2, the issue still arises. The
problem lies with how the addresses are assigned to L2 caches.
What if I have 3GB of physical memory and 3 L2 caches, with cache
responsible for 1GB of addresses? This is possible situation and we
should support it. I think the way you are using address bits is not
right. In this particular example if you use the two highest order bits,
things should work fine.
--
Nilay
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