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Review request for Default. Repository: gem5 Description ------- Adds SMT support to the "simple" CPU models so that they can be used with other SMT-supported CPUs. Example usage: have the TimingSimpleCPU warmup caches before swapping to detailed mode with the in-order or out-of-order based CPU models. Diffs ----- src/cpu/simple/base.hh 40526b73c7db9ff2e03215cdfb477d024ea8d709 src/cpu/simple/base.cc 40526b73c7db9ff2e03215cdfb477d024ea8d709 src/cpu/simple/exec_context.hh PRE-CREATION src/cpu/simple/timing.hh 40526b73c7db9ff2e03215cdfb477d024ea8d709 src/cpu/simple/timing.cc 40526b73c7db9ff2e03215cdfb477d024ea8d709 tests/quick/se/01.hello-2T-smt/test.py 40526b73c7db9ff2e03215cdfb477d024ea8d709 src/cpu/simple/atomic.hh 40526b73c7db9ff2e03215cdfb477d024ea8d709 src/cpu/simple/atomic.cc 40526b73c7db9ff2e03215cdfb477d024ea8d709 configs/example/se.py 40526b73c7db9ff2e03215cdfb477d024ea8d709 Diff: http://reviews.gem5.org/r/2995/diff/ Testing ------- Thanks, Curtis Dunham _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
