----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2995/#review7018 -----------------------------------------------------------
I have mixed feelings about this patch---on the one hand, the uniformity of all CPU models supporting SMT is nice. On the other hand, the idea of the SimpleCPU classes was for them to be simple, and this is a big step away from that. My initial thought was that you could warm up the L1 cache for a four-thread SMT detailed CPU by using four single-threaded simple CPUs, but I guess if you're in FS mode and you have some per-core (not per-thread) OS-visible state then that would get tricky. Is that the case? If we are going to stick with an SMT SimpleCPU, it would be nice to restructure things a little more, rather that just putting for loops and "tinfo." all over. For example, can we define a SimpleCPUThread object and move a lot of the code to that? That would get rid of a lot of the "tinfo." all over the place. Also, part of the idea of the SimpleCPU models is that they provide an example of the minimum that needs to be done to turn the ISA description into a functional model; if SimpleCPUThread could play that role instead, I'd feel better about the added complexity in SimpleCPU itself. Also, with all the code that's moved out of base.hh and into exec_context.hh it's hard to tell what if anything has changed there. It would be nice if that reorganization was packaged as a separate patch. - Steve Reinhardt On July 30, 2015, 11:47 a.m., Curtis Dunham wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2995/ > ----------------------------------------------------------- > > (Updated July 30, 2015, 11:47 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Adds SMT support to the "simple" CPU models so that they can be used > with other SMT-supported CPUs. Example usage: have the TimingSimpleCPU > warmup caches before swapping to detailed mode with the in-order or > out-of-order based CPU models. > > > Diffs > ----- > > src/cpu/simple/base.hh 40526b73c7db9ff2e03215cdfb477d024ea8d709 > src/cpu/simple/base.cc 40526b73c7db9ff2e03215cdfb477d024ea8d709 > src/cpu/simple/exec_context.hh PRE-CREATION > src/cpu/simple/timing.hh 40526b73c7db9ff2e03215cdfb477d024ea8d709 > src/cpu/simple/timing.cc 40526b73c7db9ff2e03215cdfb477d024ea8d709 > tests/quick/se/01.hello-2T-smt/test.py > 40526b73c7db9ff2e03215cdfb477d024ea8d709 > src/cpu/simple/atomic.hh 40526b73c7db9ff2e03215cdfb477d024ea8d709 > src/cpu/simple/atomic.cc 40526b73c7db9ff2e03215cdfb477d024ea8d709 > configs/example/se.py 40526b73c7db9ff2e03215cdfb477d024ea8d709 > > Diff: http://reviews.gem5.org/r/2995/diff/ > > > Testing > ------- > > > Thanks, > > Curtis Dunham > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
