In response to reviews http://reviews.gem5.org/r/2821/ and http://reviews.gem5.org/r/3003/.
I was going to look at addressing this today for AMD. I'm not extremely familiar with the organization of the request flags, packet commands, packet attributes, and packet flags. That said, I was under the impression that the request is supposed to capture information that exist at the instruction level. To me, acquire and release are at the instruction level (not a spurious command between two memory controllers like flush command). Also, the 32 bits that we have to work with in the request seems rather small. Especially, when you consider that it needs to capture all of the possible attributes for a memory request across all of the different ISAs... How would armv8 ldra and strl instructions convey to the cache hierarchy acquire/release attributes from the instruction (if it were necessary)? Thanks, Marc _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
