changeset 4872dbdea907 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4872dbdea907
description:
ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory
system.
This memory system would now use the type Addr that is in use by the
rest of the system.
diffstat:
src/cpu/testers/rubytest/Check.cc | 34 +-
src/cpu/testers/rubytest/Check.hh | 10 +-
src/cpu/testers/rubytest/CheckTable.cc | 26 +-
src/cpu/testers/rubytest/CheckTable.hh | 6 +-
src/cpu/testers/rubytest/RubyTester.hh | 2 +-
src/mem/protocol/MESI_Three_Level-L0cache.sm | 32 +-
src/mem/protocol/MESI_Three_Level-L1cache.sm | 28 +-
src/mem/protocol/MESI_Three_Level-msg.sm | 2 +-
src/mem/protocol/MESI_Two_Level-L1cache.sm | 32 +-
src/mem/protocol/MESI_Two_Level-L2cache.sm | 32 +-
src/mem/protocol/MESI_Two_Level-dir.sm | 26 +-
src/mem/protocol/MESI_Two_Level-dma.sm | 12 +-
src/mem/protocol/MESI_Two_Level-msg.sm | 4 +-
src/mem/protocol/MI_example-cache.sm | 22 +-
src/mem/protocol/MI_example-dir.sm | 24 +-
src/mem/protocol/MI_example-dma.sm | 12 +-
src/mem/protocol/MI_example-msg.sm | 12 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 30 +-
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 66 ++--
src/mem/protocol/MOESI_CMP_directory-dir.sm | 30 +-
src/mem/protocol/MOESI_CMP_directory-dma.sm | 22 +-
src/mem/protocol/MOESI_CMP_directory-msg.sm | 6 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 60 ++--
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 54 +-
src/mem/protocol/MOESI_CMP_token-dir.sm | 50 +-
src/mem/protocol/MOESI_CMP_token-dma.sm | 12 +-
src/mem/protocol/MOESI_CMP_token-msg.sm | 14 +-
src/mem/protocol/MOESI_hammer-cache.sm | 42 +-
src/mem/protocol/MOESI_hammer-dir.sm | 28 +-
src/mem/protocol/MOESI_hammer-dma.sm | 12 +-
src/mem/protocol/MOESI_hammer-msg.sm | 14 +-
src/mem/protocol/Network_test-cache.sm | 14 +-
src/mem/protocol/Network_test-dir.sm | 12 +-
src/mem/protocol/Network_test-msg.sm | 2 +-
src/mem/protocol/RubySlicc_ComponentMapping.sm | 10 +-
src/mem/protocol/RubySlicc_Defines.sm | 6 +-
src/mem/protocol/RubySlicc_Exports.sm | 12 +-
src/mem/protocol/RubySlicc_MemControl.sm | 2 +-
src/mem/protocol/RubySlicc_Types.sm | 88 ++--
src/mem/protocol/RubySlicc_Util.sm | 8 +-
src/mem/ruby/common/Address.cc | 179 +++++------
src/mem/ruby/common/Address.hh | 195 +------------
src/mem/ruby/common/SubBlock.cc | 6 +-
src/mem/ruby/common/SubBlock.hh | 8 +-
src/mem/ruby/common/TypeDefines.hh | 2 -
src/mem/ruby/filters/AbstractBloomFilter.hh | 14 +-
src/mem/ruby/filters/BlockBloomFilter.cc | 23 +-
src/mem/ruby/filters/BlockBloomFilter.hh | 16 +-
src/mem/ruby/filters/BulkBloomFilter.cc | 64 ++--
src/mem/ruby/filters/BulkBloomFilter.hh | 18 +-
src/mem/ruby/filters/GenericBloomFilter.cc | 14 +-
src/mem/ruby/filters/GenericBloomFilter.hh | 14 +-
src/mem/ruby/filters/H3BloomFilter.cc | 18 +-
src/mem/ruby/filters/H3BloomFilter.hh | 17 +-
src/mem/ruby/filters/LSB_CountingBloomFilter.cc | 22 +-
src/mem/ruby/filters/LSB_CountingBloomFilter.hh | 16 +-
src/mem/ruby/filters/MultiBitSelBloomFilter.cc | 18 +-
src/mem/ruby/filters/MultiBitSelBloomFilter.hh | 17 +-
src/mem/ruby/filters/MultiGrainBloomFilter.cc | 26 +-
src/mem/ruby/filters/MultiGrainBloomFilter.hh | 18 +-
src/mem/ruby/filters/NonCountingBloomFilter.cc | 22 +-
src/mem/ruby/filters/NonCountingBloomFilter.hh | 16 +-
src/mem/ruby/network/MessageBuffer.cc | 6 +-
src/mem/ruby/network/MessageBuffer.hh | 6 +-
src/mem/ruby/profiler/AccessTraceForAddress.hh | 6 +-
src/mem/ruby/profiler/AddressProfiler.cc | 15 +-
src/mem/ruby/profiler/AddressProfiler.hh | 12 +-
src/mem/ruby/profiler/StoreTrace.cc | 2 +-
src/mem/ruby/profiler/StoreTrace.hh | 4 +-
src/mem/ruby/slicc_interface/AbstractCacheEntry.cc | 2 +-
src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | 2 +-
src/mem/ruby/slicc_interface/AbstractController.cc | 29 +-
src/mem/ruby/slicc_interface/AbstractController.hh | 28 +-
src/mem/ruby/slicc_interface/RubyRequest.cc | 2 +-
src/mem/ruby/slicc_interface/RubyRequest.hh | 17 +-
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh | 8 +-
src/mem/ruby/slicc_interface/RubySlicc_Util.hh | 56 +--
src/mem/ruby/structures/CacheMemory.cc | 82 ++--
src/mem/ruby/structures/CacheMemory.hh | 46 +-
src/mem/ruby/structures/DirectoryMemory.cc | 31 +-
src/mem/ruby/structures/DirectoryMemory.hh | 19 +-
src/mem/ruby/structures/MemoryNode.hh | 6 +-
src/mem/ruby/structures/PerfectCacheMemory.hh | 55 +-
src/mem/ruby/structures/PersistentTable.cc | 36 +-
src/mem/ruby/structures/PersistentTable.hh | 20 +-
src/mem/ruby/structures/Prefetcher.cc | 78 ++--
src/mem/ruby/structures/Prefetcher.hh | 34 +-
src/mem/ruby/structures/RubyMemoryControl.cc | 12 +-
src/mem/ruby/structures/RubyMemoryControl.hh | 8 +-
src/mem/ruby/structures/TBETable.hh | 20 +-
src/mem/ruby/structures/TimerTable.cc | 12 +-
src/mem/ruby/structures/TimerTable.hh | 14 +-
src/mem/ruby/system/CacheRecorder.cc | 3 +-
src/mem/ruby/system/CacheRecorder.hh | 9 +-
src/mem/ruby/system/DMASequencer.cc | 16 +-
src/mem/ruby/system/DMASequencer.hh | 2 +-
src/mem/ruby/system/RubyPort.cc | 10 +-
src/mem/ruby/system/RubyPort.hh | 4 +-
src/mem/ruby/system/Sequencer.cc | 53 +-
src/mem/ruby/system/Sequencer.hh | 14 +-
src/mem/ruby/system/System.cc | 13 +-
src/mem/slicc/ast/ActionDeclAST.py | 4 +-
src/mem/slicc/ast/InPortDeclAST.py | 8 +-
src/mem/slicc/ast/StallAndWaitStatementAST.py | 2 +-
src/mem/slicc/symbols/StateMachine.py | 30 +-
src/mem/slicc/symbols/Type.py | 5 +-
106 files changed, 1122 insertions(+), 1372 deletions(-)
diffs (truncated from 7016 to 300 lines):
diff -r bc179fa0b91b -r 4872dbdea907 src/cpu/testers/rubytest/Check.cc
--- a/src/cpu/testers/rubytest/Check.cc Fri Aug 14 12:04:47 2015 -0500
+++ b/src/cpu/testers/rubytest/Check.cc Fri Aug 14 12:04:51 2015 -0500
@@ -34,8 +34,8 @@
typedef RubyTester::SenderState SenderState;
-Check::Check(const Address& address, const Address& pc,
- int _num_writers, int _num_readers, RubyTester* _tester)
+Check::Check(Addr address, Addr pc, int _num_writers, int _num_readers,
+ RubyTester* _tester)
: m_num_writers(_num_writers), m_num_readers(_num_readers),
m_tester_ptr(_tester)
{
@@ -103,8 +103,8 @@
}
// Prefetches are assumed to be 0 sized
- Request *req = new Request(m_address.getAddress(), 0, flags,
- m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
+ Request *req = new Request(m_address, 0, flags,
+ m_tester_ptr->masterId(), curTick(), m_pc);
req->setThreadContext(index, 0);
PacketPtr pkt = new Packet(req, cmd);
@@ -142,8 +142,8 @@
Request::Flags flags;
- Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
- m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
+ Request *req = new Request(m_address, CHECK_SIZE, flags,
+ m_tester_ptr->masterId(), curTick(), m_pc);
Packet::Command cmd;
@@ -172,12 +172,11 @@
Request::Flags flags;
// Create the particular address for the next byte to be written
- Address writeAddr(m_address.getAddress() + m_store_count);
+ Addr writeAddr(m_address + m_store_count);
// Stores are assumed to be 1 byte-sized
- Request *req = new Request(writeAddr.getAddress(), 1, flags,
- m_tester_ptr->masterId(), curTick(),
- m_pc.getAddress());
+ Request *req = new Request(writeAddr, 1, flags, m_tester_ptr->masterId(),
+ curTick(), m_pc);
req->setThreadContext(index, 0);
Packet::Command cmd;
@@ -238,8 +237,8 @@
}
// Checks are sized depending on the number of bytes written
- Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
- m_tester_ptr->masterId(), curTick(),
m_pc.getAddress());
+ Request *req = new Request(m_address, CHECK_SIZE, flags,
+ m_tester_ptr->masterId(), curTick(), m_pc);
req->setThreadContext(index, 0);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
@@ -273,12 +272,12 @@
void
Check::performCallback(NodeID proc, SubBlock* data, Cycles curTime)
{
- Address address = data->getAddress();
+ Addr address = data->getAddress();
// This isn't exactly right since we now have multi-byte checks
// assert(getAddress() == address);
- assert(getAddress().getLineAddress() == address.getLineAddress());
+ assert(makeLineAddress(m_address) == makeLineAddress(address));
assert(data != NULL);
DPRINTF(RubyTest, "RubyTester Callback\n");
@@ -325,13 +324,13 @@
}
DPRINTF(RubyTest, "proc: %d, Address: 0x%x\n", proc,
- getAddress().getLineAddress());
+ makeLineAddress(m_address));
DPRINTF(RubyTest, "Callback done\n");
debugPrint();
}
void
-Check::changeAddress(const Address& address)
+Check::changeAddress(Addr address)
{
assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready);
m_status = TesterStatus_Idle;
@@ -375,7 +374,6 @@
{
DPRINTF(RubyTest,
"[%#x, value: %d, status: %s, initiating node: %d, store_count: %d]\n",
- m_address.getAddress(), (int)m_value,
- TesterStatus_to_string(m_status).c_str(),
+ m_address, (int)m_value, TesterStatus_to_string(m_status).c_str(),
m_initiatingNode, m_store_count);
}
diff -r bc179fa0b91b -r 4872dbdea907 src/cpu/testers/rubytest/Check.hh
--- a/src/cpu/testers/rubytest/Check.hh Fri Aug 14 12:04:47 2015 -0500
+++ b/src/cpu/testers/rubytest/Check.hh Fri Aug 14 12:04:51 2015 -0500
@@ -45,13 +45,13 @@
class Check
{
public:
- Check(const Address& address, const Address& pc, int _num_writers,
+ Check(Addr address, Addr pc, int _num_writers,
int _num_readers, RubyTester* _tester);
void initiate(); // Does Action or Check or nether
void performCallback(NodeID proc, SubBlock* data, Cycles curTime);
- const Address& getAddress() { return m_address; }
- void changeAddress(const Address& address);
+ Addr getAddress() const { return m_address; }
+ void changeAddress(Addr address);
void print(std::ostream& out) const;
@@ -70,8 +70,8 @@
uint8_t m_value;
int m_store_count;
NodeID m_initiatingNode;
- Address m_address;
- Address m_pc;
+ Addr m_address;
+ Addr m_pc;
RubyAccessMode m_access_mode;
int m_num_writers;
int m_num_readers;
diff -r bc179fa0b91b -r 4872dbdea907 src/cpu/testers/rubytest/CheckTable.cc
--- a/src/cpu/testers/rubytest/CheckTable.cc Fri Aug 14 12:04:47 2015 -0500
+++ b/src/cpu/testers/rubytest/CheckTable.cc Fri Aug 14 12:04:51 2015 -0500
@@ -37,8 +37,7 @@
: m_num_writers(_num_writers), m_num_readers(_num_readers),
m_tester_ptr(_tester)
{
- physical_address_t physical = 0;
- Address address;
+ Addr physical = 0;
const int size1 = 32;
const int size2 = 100;
@@ -47,8 +46,7 @@
physical = 1000;
for (int i = 0; i < size1; i++) {
// Setup linear addresses
- address.setAddress(physical);
- addCheck(address);
+ addCheck(physical);
physical += CHECK_SIZE;
}
@@ -57,16 +55,14 @@
physical = 1000;
for (int i = 0; i < size2; i++) {
// Setup linear addresses
- address.setAddress(physical);
- addCheck(address);
+ addCheck(physical);
physical += 256;
}
physical = 1000 + CHECK_SIZE;
for (int i = 0; i < size2; i++) {
// Setup linear addresses
- address.setAddress(physical);
- addCheck(address);
+ addCheck(physical);
physical += 256;
}
}
@@ -79,27 +75,27 @@
}
void
-CheckTable::addCheck(const Address& address)
+CheckTable::addCheck(Addr address)
{
if (floorLog2(CHECK_SIZE) != 0) {
- if (address.bitSelect(0, CHECK_SIZE_BITS - 1) != 0) {
+ if (bitSelect(address, 0, CHECK_SIZE_BITS - 1) != 0) {
panic("Check not aligned");
}
}
for (int i = 0; i < CHECK_SIZE; i++) {
- if (m_lookup_map.count(Address(address.getAddress()+i))) {
+ if (m_lookup_map.count(address+i)) {
// A mapping for this byte already existed, discard the
// entire check
return;
}
}
- Check* check_ptr = new Check(address, Address(100 + m_check_vector.size()),
+ Check* check_ptr = new Check(address, 100 + m_check_vector.size(),
m_num_writers, m_num_readers, m_tester_ptr);
for (int i = 0; i < CHECK_SIZE; i++) {
// Insert it once per byte
- m_lookup_map[Address(address.getAddress() + i)] = check_ptr;
+ m_lookup_map[address + i] = check_ptr;
}
m_check_vector.push_back(check_ptr);
}
@@ -112,11 +108,11 @@
}
Check*
-CheckTable::getCheck(const Address& address)
+CheckTable::getCheck(const Addr address)
{
DPRINTF(RubyTest, "Looking for check by address: %s", address);
- m5::hash_map<Address, Check*>::iterator i = m_lookup_map.find(address);
+ m5::hash_map<Addr, Check*>::iterator i = m_lookup_map.find(address);
if (i == m_lookup_map.end())
return NULL;
diff -r bc179fa0b91b -r 4872dbdea907 src/cpu/testers/rubytest/CheckTable.hh
--- a/src/cpu/testers/rubytest/CheckTable.hh Fri Aug 14 12:04:47 2015 -0500
+++ b/src/cpu/testers/rubytest/CheckTable.hh Fri Aug 14 12:04:51 2015 -0500
@@ -46,7 +46,7 @@
~CheckTable();
Check* getRandomCheck();
- Check* getCheck(const Address& address);
+ Check* getCheck(Addr address);
// bool isPresent(const Address& address) const;
// void removeCheckFromTable(const Address& address);
@@ -56,14 +56,14 @@
void print(std::ostream& out) const;
private:
- void addCheck(const Address& address);
+ void addCheck(Addr address);
// Private copy constructor and assignment operator
CheckTable(const CheckTable& obj);
CheckTable& operator=(const CheckTable& obj);
std::vector<Check*> m_check_vector;
- m5::hash_map<Address, Check*> m_lookup_map;
+ m5::hash_map<Addr, Check*> m_lookup_map;
int m_num_writers;
int m_num_readers;
diff -r bc179fa0b91b -r 4872dbdea907 src/cpu/testers/rubytest/RubyTester.hh
--- a/src/cpu/testers/rubytest/RubyTester.hh Fri Aug 14 12:04:47 2015 -0500
+++ b/src/cpu/testers/rubytest/RubyTester.hh Fri Aug 14 12:04:51 2015 -0500
@@ -82,7 +82,7 @@
{
SubBlock subBlock;
- SenderState(Address addr, int size) : subBlock(addr, size) {}
+ SenderState(Addr addr, int size) : subBlock(addr, size) {}
};
diff -r bc179fa0b91b -r 4872dbdea907
src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Fri Aug 14 12:04:47
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Fri Aug 14 12:04:51
2015 -0500
@@ -119,7 +119,7 @@
// TBE fields
structure(TBE, desc="...") {
- Address addr, desc="Physical address for this TBE";
+ Addr addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
DataBlock DataBlk, desc="Buffer for the data block";
bool Dirty, default="false", desc="data is dirty";
@@ -127,10 +127,10 @@
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
TBETable TBEs, template="<L0Cache_TBE>", constructor="m_number_of_TBEs";
@@ -139,12 +139,12 @@
void unset_cache_entry();
void set_tbe(TBE a);
void unset_tbe();
- void wakeUpBuffers(Address a);
- void wakeUpAllBuffers(Address a);
+ void wakeUpBuffers(Addr a);
+ void wakeUpAllBuffers(Addr a);
void profileMsgDelay(int virtualNetworkType, Cycles c);
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