changeset bc179fa0b91b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bc179fa0b91b
description:
ruby: rename variables Addr to addr
Avoid clash between type Addr and variable name Addr.
diffstat:
src/mem/protocol/MESI_Three_Level-L0cache.sm | 36 +-
src/mem/protocol/MESI_Three_Level-L1cache.sm | 94 ++++----
src/mem/protocol/MESI_Three_Level-msg.sm | 6 +-
src/mem/protocol/MESI_Two_Level-L1cache.sm | 80 +++---
src/mem/protocol/MESI_Two_Level-L2cache.sm | 90 ++++----
src/mem/protocol/MESI_Two_Level-dir.sm | 36 +-
src/mem/protocol/MESI_Two_Level-dma.sm | 8 +-
src/mem/protocol/MESI_Two_Level-msg.sm | 12 +-
src/mem/protocol/MI_example-cache.sm | 30 +-
src/mem/protocol/MI_example-dir.sm | 34 +-
src/mem/protocol/MI_example-msg.sm | 12 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 98 ++++----
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 212 ++++++++++----------
src/mem/protocol/MOESI_CMP_directory-dir.sm | 86 ++++----
src/mem/protocol/MOESI_CMP_directory-dma.sm | 22 +-
src/mem/protocol/MOESI_CMP_directory-msg.sm | 14 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 126 ++++++------
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 130 ++++++------
src/mem/protocol/MOESI_CMP_token-dir.sm | 104 +++++-----
src/mem/protocol/MOESI_CMP_token-msg.sm | 10 +-
src/mem/protocol/MOESI_hammer-cache.sm | 102 +++++-----
src/mem/protocol/MOESI_hammer-dir.sm | 118 +++++-----
src/mem/protocol/MOESI_hammer-msg.sm | 10 +-
src/mem/protocol/Network_test-cache.sm | 6 +-
src/mem/protocol/Network_test-dir.sm | 6 +-
src/mem/protocol/Network_test-msg.sm | 2 +-
src/mem/protocol/RubySlicc_MemControl.sm | 6 +-
src/mem/ruby/slicc_interface/AbstractController.cc | 2 +-
28 files changed, 746 insertions(+), 746 deletions(-)
diffs (truncated from 4614 to 300 lines):
diff -r 97cf7ba82f0c -r bc179fa0b91b
src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Fri Aug 14 01:19:34
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Fri Aug 14 12:04:47
2015 -0500
@@ -119,7 +119,7 @@
// TBE fields
structure(TBE, desc="...") {
- Address Addr, desc="Physical address for this TBE";
+ Address addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
DataBlock DataBlk, desc="Buffer for the data block";
bool Dirty, default="false", desc="data is dirty";
@@ -256,30 +256,30 @@
// Messages for this L0 cache from the L1 cache
in_port(messgeBuffer_in, CoherenceMsg, bufferFromL1, rank = 1) {
if (messgeBuffer_in.isReady()) {
- peek(messgeBuffer_in, CoherenceMsg, block_on="Addr") {
+ peek(messgeBuffer_in, CoherenceMsg, block_on="addr") {
assert(in_msg.Dest == machineID);
- Entry cache_entry := getCacheEntry(in_msg.Addr);
- TBE tbe := TBEs[in_msg.Addr];
+ Entry cache_entry := getCacheEntry(in_msg.addr);
+ TBE tbe := TBEs[in_msg.addr];
if(in_msg.Class == CoherenceClass:DATA_EXCLUSIVE) {
- trigger(Event:Data_Exclusive, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Data_Exclusive, in_msg.addr, cache_entry, tbe);
} else if(in_msg.Class == CoherenceClass:DATA) {
- trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Data, in_msg.addr, cache_entry, tbe);
} else if (in_msg.Class == CoherenceClass:ACK) {
- trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Ack, in_msg.addr, cache_entry, tbe);
} else if (in_msg.Class == CoherenceClass:WB_ACK) {
- trigger(Event:WB_Ack, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:WB_Ack, in_msg.addr, cache_entry, tbe);
} else if (in_msg.Class == CoherenceClass:INV) {
- trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Inv, in_msg.addr, cache_entry, tbe);
} else if (in_msg.Class == CoherenceClass:GETX ||
in_msg.Class == CoherenceClass:UPGRADE) {
// upgrade transforms to GETX due to race
- trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Fwd_GETX, in_msg.addr, cache_entry, tbe);
} else if (in_msg.Class == CoherenceClass:GETS) {
- trigger(Event:Fwd_GETS, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Fwd_GETS, in_msg.addr, cache_entry, tbe);
} else if (in_msg.Class == CoherenceClass:GET_INSTR) {
- trigger(Event:Fwd_GET_INSTR, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Fwd_GET_INSTR, in_msg.addr, cache_entry, tbe);
} else {
error("Invalid forwarded request type");
}
@@ -363,7 +363,7 @@
action(a_issueGETS, "a", desc="Issue GETS") {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestNetwork_out, CoherenceMsg, request_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Class := CoherenceClass:GETS;
out_msg.Sender := machineID;
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
@@ -378,7 +378,7 @@
action(b_issueGETX, "b", desc="Issue GETX") {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestNetwork_out, CoherenceMsg, request_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Class := CoherenceClass:GETX;
out_msg.Sender := machineID;
DPRINTF(RubySlicc, "%s\n", machineID);
@@ -395,7 +395,7 @@
action(c_issueUPGRADE, "c", desc="Issue GETX") {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestNetwork_out, CoherenceMsg, request_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Class := CoherenceClass:UPGRADE;
out_msg.Sender := machineID;
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
@@ -411,7 +411,7 @@
action(f_sendDataToL1, "f", desc="send data to the L2 cache") {
enqueue(requestNetwork_out, CoherenceMsg, response_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Class := CoherenceClass:INV_DATA;
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
@@ -425,7 +425,7 @@
action(fi_sendInvAck, "fi", desc="send data to the L2 cache") {
peek(messgeBuffer_in, CoherenceMsg) {
enqueue(requestNetwork_out, CoherenceMsg, response_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Class := CoherenceClass:INV_ACK;
out_msg.Sender := machineID;
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
@@ -444,7 +444,7 @@
action(g_issuePUTX, "g", desc="send data to the L2 cache") {
enqueue(requestNetwork_out, CoherenceMsg, response_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Class := CoherenceClass:PUTX;
out_msg.Dirty := cache_entry.Dirty;
out_msg.Sender:= machineID;
diff -r 97cf7ba82f0c -r bc179fa0b91b
src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm Fri Aug 14 01:19:34
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm Fri Aug 14 12:04:47
2015 -0500
@@ -133,7 +133,7 @@
// TBE fields
structure(TBE, desc="...") {
- Address Addr, desc="Physical address for this TBE";
+ Address addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
DataBlock DataBlk, desc="Buffer for the data block";
bool Dirty, default="false", desc="data is dirty";
@@ -270,30 +270,30 @@
peek(responseNetwork_in, ResponseMsg) {
assert(in_msg.Destination.isElement(machineID));
- Entry cache_entry := getCacheEntry(in_msg.Addr);
- TBE tbe := TBEs[in_msg.Addr];
+ Entry cache_entry := getCacheEntry(in_msg.addr);
+ TBE tbe := TBEs[in_msg.addr];
if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
- trigger(Event:Data_Exclusive, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Data_Exclusive, in_msg.addr, cache_entry, tbe);
} else if(in_msg.Type == CoherenceResponseType:DATA) {
- if (getState(tbe, cache_entry, in_msg.Addr) == State:IS &&
+ if (getState(tbe, cache_entry, in_msg.addr) == State:IS &&
machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
- trigger(Event:DataS_fromL1, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:DataS_fromL1, in_msg.addr, cache_entry, tbe);
} else if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
- trigger(Event:Data_all_Acks, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Data_all_Acks, in_msg.addr, cache_entry, tbe);
} else {
- trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Data, in_msg.addr, cache_entry, tbe);
}
} else if (in_msg.Type == CoherenceResponseType:ACK) {
if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
- trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Ack_all, in_msg.addr, cache_entry, tbe);
} else {
- trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Ack, in_msg.addr, cache_entry, tbe);
}
} else if (in_msg.Type == CoherenceResponseType:WB_ACK) {
- trigger(Event:WB_Ack, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:WB_Ack, in_msg.addr, cache_entry, tbe);
} else {
error("Invalid L1 response type");
}
@@ -306,30 +306,30 @@
if(requestNetwork_in.isReady()) {
peek(requestNetwork_in, RequestMsg) {
assert(in_msg.Destination.isElement(machineID));
- Entry cache_entry := getCacheEntry(in_msg.Addr);
- TBE tbe := TBEs[in_msg.Addr];
+ Entry cache_entry := getCacheEntry(in_msg.addr);
+ TBE tbe := TBEs[in_msg.addr];
if (in_msg.Type == CoherenceRequestType:INV) {
if (is_valid(cache_entry) && inL0Cache(cache_entry.CacheState)) {
- trigger(Event:L0_Invalidate_Else, in_msg.Addr,
+ trigger(Event:L0_Invalidate_Else, in_msg.addr,
cache_entry, tbe);
} else {
- trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Inv, in_msg.addr, cache_entry, tbe);
}
} else if (in_msg.Type == CoherenceRequestType:GETX ||
in_msg.Type == CoherenceRequestType:UPGRADE) {
if (is_valid(cache_entry) && inL0Cache(cache_entry.CacheState)) {
- trigger(Event:L0_Invalidate_Else, in_msg.Addr,
+ trigger(Event:L0_Invalidate_Else, in_msg.addr,
cache_entry, tbe);
} else {
- trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Fwd_GETX, in_msg.addr, cache_entry, tbe);
}
} else if (in_msg.Type == CoherenceRequestType:GETS) {
if (is_valid(cache_entry) && inL0Cache(cache_entry.CacheState)) {
- trigger(Event:L0_Invalidate_Else, in_msg.Addr,
+ trigger(Event:L0_Invalidate_Else, in_msg.addr,
cache_entry, tbe);
} else {
- trigger(Event:Fwd_GETS, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Fwd_GETS, in_msg.addr, cache_entry, tbe);
}
} else {
error("Invalid forwarded request type");
@@ -342,36 +342,36 @@
in_port(messageBufferFromL0_in, CoherenceMsg, bufferFromL0, rank = 0) {
if (messageBufferFromL0_in.isReady()) {
peek(messageBufferFromL0_in, CoherenceMsg) {
- Entry cache_entry := getCacheEntry(in_msg.Addr);
- TBE tbe := TBEs[in_msg.Addr];
+ Entry cache_entry := getCacheEntry(in_msg.addr);
+ TBE tbe := TBEs[in_msg.addr];
if(in_msg.Class == CoherenceClass:INV_DATA) {
- trigger(Event:L0_DataAck, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:L0_DataAck, in_msg.addr, cache_entry, tbe);
} else if (in_msg.Class == CoherenceClass:INV_ACK) {
- trigger(Event:L0_Ack, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:L0_Ack, in_msg.addr, cache_entry, tbe);
} else {
if (is_valid(cache_entry)) {
trigger(mandatory_request_type_to_event(in_msg.Class),
- in_msg.Addr, cache_entry, tbe);
+ in_msg.addr, cache_entry, tbe);
} else {
- if (cache.cacheAvail(in_msg.Addr)) {
+ if (cache.cacheAvail(in_msg.addr)) {
// L1 does't have the line, but we have space for it
// in the L1 let's see if the L2 has it
trigger(mandatory_request_type_to_event(in_msg.Class),
- in_msg.Addr, cache_entry, tbe);
+ in_msg.addr, cache_entry, tbe);
} else {
// No room in the L1, so we need to make room in the L1
Entry victim_entry :=
- getCacheEntry(cache.cacheProbe(in_msg.Addr));
- TBE victim_tbe := TBEs[cache.cacheProbe(in_msg.Addr)];
+ getCacheEntry(cache.cacheProbe(in_msg.addr));
+ TBE victim_tbe := TBEs[cache.cacheProbe(in_msg.addr)];
if (is_valid(victim_entry) &&
inL0Cache(victim_entry.CacheState)) {
trigger(Event:L0_Invalidate_Own,
- cache.cacheProbe(in_msg.Addr),
+ cache.cacheProbe(in_msg.addr),
victim_entry, victim_tbe);
} else {
trigger(Event:L1_Replacement,
- cache.cacheProbe(in_msg.Addr),
+ cache.cacheProbe(in_msg.addr),
victim_entry, victim_tbe);
}
}
@@ -385,7 +385,7 @@
action(a_issueGETS, "a", desc="Issue GETS") {
peek(messageBufferFromL0_in, CoherenceMsg) {
enqueue(requestNetwork_out, RequestMsg, l1_request_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -401,7 +401,7 @@
action(b_issueGETX, "b", desc="Issue GETX") {
peek(messageBufferFromL0_in, CoherenceMsg) {
enqueue(requestNetwork_out, RequestMsg, l1_request_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceRequestType:GETX;
out_msg.Requestor := machineID;
DPRINTF(RubySlicc, "%s\n", machineID);
@@ -418,7 +418,7 @@
action(c_issueUPGRADE, "c", desc="Issue GETX") {
peek(messageBufferFromL0_in, CoherenceMsg) {
enqueue(requestNetwork_out, RequestMsg, l1_request_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceRequestType:UPGRADE;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -435,7 +435,7 @@
peek(requestNetwork_in, RequestMsg) {
enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
@@ -449,7 +449,7 @@
action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M
downgrade") {
enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
@@ -464,7 +464,7 @@
peek(requestNetwork_in, RequestMsg) {
enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) {
assert(is_valid(tbe));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
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