changeset a8a64cca231b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a8a64cca231b
description:
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
diffstat:
configs/example/fs.py | 6 ++--
configs/example/se.py | 6 ++--
src/arch/alpha/isa/decoder.isa | 2 +-
src/arch/arm/faults.cc | 8 +++---
src/arch/arm/isa.cc | 6 ++--
src/arch/arm/isa/insts/misc.isa | 11 +++++----
src/arch/sparc/isa.cc | 4 +-
src/arch/sparc/tlb.cc | 12 +++++-----
src/arch/sparc/ua2005.cc | 32 +++++++++++++-------------
src/arch/x86/utility.cc | 2 +-
src/cpu/BaseCPU.py | 40 +++++++++++++++++----------------
src/cpu/base.cc | 17 ++++++++-----
src/cpu/base.hh | 24 +++++++++++--------
src/cpu/dummy_checker.cc | 1 -
src/cpu/intr_control.cc | 4 +-
src/cpu/kvm/x86_cpu.cc | 12 +++++-----
src/cpu/minor/execute.cc | 6 ++--
src/cpu/o3/checker.cc | 1 -
src/cpu/o3/cpu.cc | 6 ++--
src/cpu/simple/base.cc | 4 +-
src/dev/x86/i82094aa.cc | 2 +-
tests/configs/pc-simple-timing-ruby.py | 6 ++--
util/cpt_upgraders/smt-interrupts.py | 19 ++++++++++++++++
23 files changed, 129 insertions(+), 102 deletions(-)
diffs (truncated from 720 to 300 lines):
diff -r c94e36977904 -r a8a64cca231b configs/example/fs.py
--- a/configs/example/fs.py Wed Sep 30 11:14:19 2015 -0500
+++ b/configs/example/fs.py Wed Sep 30 11:14:19 2015 -0500
@@ -176,9 +176,9 @@
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
- cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
- cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
- cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
+ cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
+ cpu.interrupts[0].int_master =
test_sys.ruby._cpu_ports[i].slave
+ cpu.interrupts[0].int_slave =
test_sys.ruby._cpu_ports[i].master
else:
if options.caches or options.l2cache:
diff -r c94e36977904 -r a8a64cca231b configs/example/se.py
--- a/configs/example/se.py Wed Sep 30 11:14:19 2015 -0500
+++ b/configs/example/se.py Wed Sep 30 11:14:19 2015 -0500
@@ -265,9 +265,9 @@
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
if buildEnv['TARGET_ISA'] == 'x86':
- system.cpu[i].interrupts.pio = ruby_port.master
- system.cpu[i].interrupts.int_master = ruby_port.slave
- system.cpu[i].interrupts.int_slave = ruby_port.master
+ system.cpu[i].interrupts[0].pio = ruby_port.master
+ system.cpu[i].interrupts[0].int_master = ruby_port.slave
+ system.cpu[i].interrupts[0].int_slave = ruby_port.master
system.cpu[i].itb.walker.port = ruby_port.slave
system.cpu[i].dtb.walker.port = ruby_port.slave
else:
diff -r c94e36977904 -r a8a64cca231b src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa Wed Sep 30 11:14:19 2015 -0500
+++ b/src/arch/alpha/isa/decoder.isa Wed Sep 30 11:14:19 2015 -0500
@@ -943,7 +943,7 @@
0x01: quiesce({{
// Don't sleep if (unmasked) interrupts are pending
Interrupts* interrupts =
- xc->tcBase()->getCpuPtr()->getInterruptController();
+ xc->tcBase()->getCpuPtr()->getInterruptController(0);
if (interrupts->checkInterrupts(xc->tcBase())) {
PseudoInst::quiesceSkip(xc->tcBase());
} else {
diff -r c94e36977904 -r a8a64cca231b src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/arch/arm/faults.cc Wed Sep 30 11:14:19 2015 -0500
@@ -681,7 +681,7 @@
Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
- tc->getCpuPtr()->clearInterrupts();
+ tc->getCpuPtr()->clearInterrupts(tc->threadId());
tc->clearArchRegs();
}
if (!ArmSystem::highestELIs64(tc)) {
@@ -938,7 +938,7 @@
}
if (source == ArmFault::AsynchronousExternalAbort) {
- tc->getCpuPtr()->clearInterrupt(INT_ABT, 0);
+ tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
}
// Get effective fault source encoding
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
@@ -1353,7 +1353,7 @@
void
SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
- tc->getCpuPtr()->clearInterrupt(INT_ABT, 0);
+ tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
ArmFault::invoke(tc, inst);
}
@@ -1404,7 +1404,7 @@
// SEV execution and let pipeline continue as pcState is still
// valid.
tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
- tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
+ tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0);
}
// Instantiate all the templates to make the linker happy
diff -r c94e36977904 -r a8a64cca231b src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/arch/arm/isa.cc Wed Sep 30 11:14:19 2015 -0500
@@ -668,12 +668,12 @@
case MISCREG_DBGDSCRint:
return 0;
case MISCREG_ISR:
- return tc->getCpuPtr()->getInterruptController()->getISR(
+ return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
readMiscRegNoEffect(MISCREG_HCR),
readMiscRegNoEffect(MISCREG_CPSR),
readMiscRegNoEffect(MISCREG_SCR));
case MISCREG_ISR_EL1:
- return tc->getCpuPtr()->getInterruptController()->getISR(
+ return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
readMiscRegNoEffect(MISCREG_HCR_EL2),
readMiscRegNoEffect(MISCREG_CPSR),
readMiscRegNoEffect(MISCREG_SCR_EL3));
@@ -1929,7 +1929,7 @@
"been configured to use a generic timer.\n");
}
- timer.reset(new GenericTimerISA(*generic_timer, tc->cpuId()));
+ timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
return *timer.get();
}
diff -r c94e36977904 -r a8a64cca231b src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa Wed Sep 30 11:14:19 2015 -0500
+++ b/src/arch/arm/isa/insts/misc.isa Wed Sep 30 11:14:19 2015 -0500
@@ -649,7 +649,8 @@
if (SevMailbox == 1) {
SevMailbox = 0;
PseudoInst::quiesceSkip(tc);
- } else if (tc->getCpuPtr()->getInterruptController()->checkInterrupts(tc))
{
+ } else if (tc->getCpuPtr()->getInterruptController(
+ tc->threadId())->checkInterrupts(tc)) {
PseudoInst::quiesceSkip(tc);
} else if (cpsr.el == EL0 && !sctlr.ntwe) {
PseudoInst::quiesceSkip(tc);
@@ -692,8 +693,8 @@
// WFI doesn't sleep if interrupts are pending (masked or not)
ThreadContext *tc = xc->tcBase();
- if (tc->getCpuPtr()->getInterruptController()->checkWfiWake(hcr, cpsr,
- scr)) {
+ if (tc->getCpuPtr()->getInterruptController(
+ tc->threadId())->checkWfiWake(hcr, cpsr, scr)) {
PseudoInst::quiesceSkip(tc);
} else if (cpsr.el == EL0 && !sctlr.ntwi) {
PseudoInst::quiesceSkip(tc);
@@ -711,7 +712,7 @@
} else {
PseudoInst::quiesce(tc);
}
- tc->getCpuPtr()->clearInterrupt(INT_ABT, 0);
+ tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
'''
wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
{ "code" : wfiCode, "predicate_test" : predicateTest },
@@ -731,7 +732,7 @@
// Wake CPU with interrupt if they were sleeping
if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
// Post Interrupt and wake cpu if needed
- oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
+ oc->getCpuPtr()->postInterrupt(oc->threadId(), INT_SEV, 0);
}
}
'''
diff -r c94e36977904 -r a8a64cca231b src/arch/sparc/isa.cc
--- a/src/arch/sparc/isa.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/arch/sparc/isa.cc Wed Sep 30 11:14:19 2015 -0500
@@ -591,9 +591,9 @@
{
tl = val;
if (hpstate.tlz && tl == 0 && !hpstate.hpriv)
- tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
+ tc->getCpuPtr()->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
else
- tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
+ tc->getCpuPtr()->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
return;
}
case MISCREG_CWP:
diff -r c94e36977904 -r a8a64cca231b src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/arch/sparc/tlb.cc Wed Sep 30 11:14:19 2015 -0500
@@ -1022,7 +1022,7 @@
{
SparcISA::Interrupts * interrupts =
dynamic_cast<SparcISA::Interrupts *>(
- tc->getCpuPtr()->getInterruptController());
+ tc->getCpuPtr()->getInterruptController(0));
pkt->set(interrupts->get_vec(IT_INT_VEC));
}
break;
@@ -1030,9 +1030,9 @@
{
SparcISA::Interrupts * interrupts =
dynamic_cast<SparcISA::Interrupts *>(
- tc->getCpuPtr()->getInterruptController());
+ tc->getCpuPtr()->getInterruptController(0));
temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
- tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp);
+ tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp);
pkt->set(temp);
}
break;
@@ -1278,16 +1278,16 @@
// clear all the interrupts that aren't set in the write
SparcISA::Interrupts * interrupts =
dynamic_cast<SparcISA::Interrupts *>(
- tc->getCpuPtr()->getInterruptController());
+ tc->getCpuPtr()->getInterruptController(0));
while (interrupts->get_vec(IT_INT_VEC) & data) {
msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
- tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb);
+ tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb);
}
}
break;
case ASI_SWVR_UDB_INTR_W:
tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
- postInterrupt(bits(data, 5, 0), 0);
+ postInterrupt(0, bits(data, 5, 0), 0);
break;
default:
doMmuWriteError:
diff -r c94e36977904 -r a8a64cca231b src/arch/sparc/ua2005.cc
--- a/src/arch/sparc/ua2005.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/arch/sparc/ua2005.cc Wed Sep 30 11:14:19 2015 -0500
@@ -49,20 +49,20 @@
// If PIL < 14, copy over the tm and sm bits
if (pil < 14 && softint & 0x10000)
- cpu->postInterrupt(IT_SOFT_INT, 16);
+ cpu->postInterrupt(0, IT_SOFT_INT, 16);
else
- cpu->clearInterrupt(IT_SOFT_INT, 16);
+ cpu->clearInterrupt(0, IT_SOFT_INT, 16);
if (pil < 14 && softint & 0x1)
- cpu->postInterrupt(IT_SOFT_INT, 0);
+ cpu->postInterrupt(0, IT_SOFT_INT, 0);
else
- cpu->clearInterrupt(IT_SOFT_INT, 0);
+ cpu->clearInterrupt(0, IT_SOFT_INT, 0);
// Copy over any of the other bits that are set
for (int bit = 15; bit > 0; --bit) {
if (1 << bit & softint && bit > pil)
- cpu->postInterrupt(IT_SOFT_INT, bit);
+ cpu->postInterrupt(0, IT_SOFT_INT, bit);
else
- cpu->clearInterrupt(IT_SOFT_INT, bit);
+ cpu->clearInterrupt(0, IT_SOFT_INT, bit);
}
}
@@ -149,9 +149,9 @@
case MISCREG_HINTP:
setMiscRegNoEffect(miscReg, val);
if (hintp)
- cpu->postInterrupt(IT_HINTP, 0);
+ cpu->postInterrupt(0, IT_HINTP, 0);
else
- cpu->clearInterrupt(IT_HINTP, 0);
+ cpu->clearInterrupt(0, IT_HINTP, 0);
break;
case MISCREG_HTBA:
@@ -163,25 +163,25 @@
case MISCREG_QUEUE_CPU_MONDO_TAIL:
setMiscRegNoEffect(miscReg, val);
if (cpu_mondo_head != cpu_mondo_tail)
- cpu->postInterrupt(IT_CPU_MONDO, 0);
+ cpu->postInterrupt(0, IT_CPU_MONDO, 0);
else
- cpu->clearInterrupt(IT_CPU_MONDO, 0);
+ cpu->clearInterrupt(0, IT_CPU_MONDO, 0);
break;
case MISCREG_QUEUE_DEV_MONDO_HEAD:
case MISCREG_QUEUE_DEV_MONDO_TAIL:
setMiscRegNoEffect(miscReg, val);
if (dev_mondo_head != dev_mondo_tail)
- cpu->postInterrupt(IT_DEV_MONDO, 0);
+ cpu->postInterrupt(0, IT_DEV_MONDO, 0);
else
- cpu->clearInterrupt(IT_DEV_MONDO, 0);
+ cpu->clearInterrupt(0, IT_DEV_MONDO, 0);
break;
case MISCREG_QUEUE_RES_ERROR_HEAD:
case MISCREG_QUEUE_RES_ERROR_TAIL:
setMiscRegNoEffect(miscReg, val);
if (res_error_head != res_error_tail)
- cpu->postInterrupt(IT_RES_ERROR, 0);
+ cpu->postInterrupt(0, IT_RES_ERROR, 0);
else
- cpu->clearInterrupt(IT_RES_ERROR, 0);
+ cpu->clearInterrupt(0, IT_RES_ERROR, 0);
break;
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
@@ -213,9 +213,9 @@
setMiscRegNoEffect(miscReg, newVal);
newVal = hpstate;
if (newVal.tlz && tl == 0 && !newVal.hpriv)
- cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
+ cpu->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
else
- cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
+ cpu->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
break;
}
case MISCREG_HTSTATE:
diff -r c94e36977904 -r a8a64cca231b src/arch/x86/utility.cc
--- a/src/arch/x86/utility.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/arch/x86/utility.cc Wed Sep 30 11:14:19 2015 -0500
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
