changeset ca4ea9b5c052 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ca4ea9b5c052
description:
cpu,isa,mem: Add per-thread wakeup logic
Changes wakeup functionality so that only specific threads on SMT
capable cpus are woken.
diffstat:
src/arch/arm/locked_mem.hh | 2 +-
src/arch/null/cpu_dummy.hh | 2 +-
src/arch/x86/interrupts.cc | 2 +-
src/cpu/base.hh | 4 ++--
src/cpu/checker/cpu.hh | 2 +-
src/cpu/kvm/base.cc | 2 +-
src/cpu/kvm/base.hh | 2 +-
src/cpu/minor/cpu.cc | 13 ++++++-------
src/cpu/minor/cpu.hh | 2 +-
src/cpu/o3/cpu.cc | 8 ++++----
src/cpu/o3/cpu.hh | 2 +-
src/cpu/simple/atomic.cc | 6 +++---
src/cpu/simple/base.cc | 13 ++++++-------
src/cpu/simple/base.hh | 2 +-
src/cpu/simple/timing.cc | 6 +++---
src/mem/abstract_mem.cc | 3 ++-
16 files changed, 35 insertions(+), 36 deletions(-)
diffs (288 lines):
diff -r a8a64cca231b -r ca4ea9b5c052 src/arch/arm/locked_mem.hh
--- a/src/arch/arm/locked_mem.hh Wed Sep 30 11:14:19 2015 -0500
+++ b/src/arch/arm/locked_mem.hh Wed Sep 30 11:14:19 2015 -0500
@@ -82,7 +82,7 @@
xc->setMiscReg(MISCREG_LOCKFLAG, false);
// Implement ARMv8 WFE/SEV semantics
xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
- xc->getCpuPtr()->wakeup();
+ xc->getCpuPtr()->wakeup(xc->threadId());
}
}
diff -r a8a64cca231b -r ca4ea9b5c052 src/arch/null/cpu_dummy.hh
--- a/src/arch/null/cpu_dummy.hh Wed Sep 30 11:14:19 2015 -0500
+++ b/src/arch/null/cpu_dummy.hh Wed Sep 30 11:14:19 2015 -0500
@@ -47,7 +47,7 @@
public:
static int numSimulatedInsts() { return 0; }
static int numSimulatedOps() { return 0; }
- static void wakeup() { ; }
+ static void wakeup(ThreadID tid) { ; }
};
#endif // __ARCH_NULL_CPU_DUMMY_HH__
diff -r a8a64cca231b -r ca4ea9b5c052 src/arch/x86/interrupts.cc
--- a/src/arch/x86/interrupts.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/arch/x86/interrupts.cc Wed Sep 30 11:14:19 2015 -0500
@@ -290,7 +290,7 @@
}
}
if (FullSystem)
- cpu->wakeup();
+ cpu->wakeup(0);
}
diff -r a8a64cca231b -r ca4ea9b5c052 src/cpu/base.hh
--- a/src/cpu/base.hh Wed Sep 30 11:14:19 2015 -0500
+++ b/src/cpu/base.hh Wed Sep 30 11:14:19 2015 -0500
@@ -220,14 +220,14 @@
return interrupts[tid];
}
- virtual void wakeup() = 0;
+ virtual void wakeup(ThreadID tid) = 0;
void
postInterrupt(ThreadID tid, int int_num, int index)
{
interrupts[tid]->post(int_num, index);
if (FullSystem)
- wakeup();
+ wakeup(tid);
}
void
diff -r a8a64cca231b -r ca4ea9b5c052 src/cpu/checker/cpu.hh
--- a/src/cpu/checker/cpu.hh Wed Sep 30 11:14:19 2015 -0500
+++ b/src/cpu/checker/cpu.hh Wed Sep 30 11:14:19 2015 -0500
@@ -380,7 +380,7 @@
Fault hwrei() { return thread->hwrei(); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
- void wakeup() { }
+ void wakeup(ThreadID tid) M5_ATTR_OVERRIDE { }
// Assume that the normal CPU's call to syscall was successful.
// The checker's state would have already been updated by the syscall.
void syscall(int64_t callnum) { }
diff -r a8a64cca231b -r ca4ea9b5c052 src/cpu/kvm/base.cc
--- a/src/cpu/kvm/base.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/cpu/kvm/base.cc Wed Sep 30 11:14:19 2015 -0500
@@ -408,7 +408,7 @@
}
void
-BaseKvmCPU::wakeup()
+BaseKvmCPU::wakeup(ThreadID tid)
{
DPRINTF(Kvm, "wakeup()\n");
// This method might have been called from another
diff -r a8a64cca231b -r ca4ea9b5c052 src/cpu/kvm/base.hh
--- a/src/cpu/kvm/base.hh Wed Sep 30 11:14:19 2015 -0500
+++ b/src/cpu/kvm/base.hh Wed Sep 30 11:14:19 2015 -0500
@@ -100,7 +100,7 @@
MasterPort &getDataPort() { return dataPort; }
MasterPort &getInstPort() { return instPort; }
- void wakeup();
+ void wakeup(ThreadID tid = 0) M5_ATTR_OVERRIDE;
void activateContext(ThreadID thread_num);
void suspendContext(ThreadID thread_num);
void deallocateContext(ThreadID thread_num);
diff -r a8a64cca231b -r ca4ea9b5c052 src/cpu/minor/cpu.cc
--- a/src/cpu/minor/cpu.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/cpu/minor/cpu.cc Wed Sep 30 11:14:19 2015 -0500
@@ -167,14 +167,12 @@
}
void
-MinorCPU::wakeup()
+MinorCPU::wakeup(ThreadID tid)
{
- DPRINTF(Drain, "MinorCPU wakeup\n");
+ DPRINTF(Drain, "[tid:%d] MinorCPU wakeup\n", tid);
- for (auto i = threads.begin(); i != threads.end(); i ++) {
- if ((*i)->status() == ThreadContext::Suspended)
- (*i)->activate();
- }
+ if (threads[tid]->status() == ThreadContext::Suspended)
+ threads[tid]->activate();
DPRINTF(Drain,"Suspended Processor awoke\n");
}
@@ -241,7 +239,8 @@
"'timing' mode.\n");
}
- wakeup();
+ for (ThreadID tid = 0; tid < numThreads; tid++)
+ wakeup(tid);
pipeline->drainResume();
}
diff -r a8a64cca231b -r ca4ea9b5c052 src/cpu/minor/cpu.hh
--- a/src/cpu/minor/cpu.hh Wed Sep 30 11:14:19 2015 -0500
+++ b/src/cpu/minor/cpu.hh Wed Sep 30 11:14:19 2015 -0500
@@ -128,7 +128,7 @@
/** Starting, waking and initialisation */
void init();
void startup();
- void wakeup();
+ void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
Addr dbg_vtophys(Addr addr);
diff -r a8a64cca231b -r ca4ea9b5c052 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/cpu/o3/cpu.cc Wed Sep 30 11:14:19 2015 -0500
@@ -120,7 +120,7 @@
{
for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
- cpu->wakeup();
+ cpu->wakeup(tid);
}
}
lsq->recvTimingSnoopReq(pkt);
@@ -1633,15 +1633,15 @@
template <class Impl>
void
-FullO3CPU<Impl>::wakeup()
+FullO3CPU<Impl>::wakeup(ThreadID tid)
{
- if (this->thread[0]->status() != ThreadContext::Suspended)
+ if (this->thread[tid]->status() != ThreadContext::Suspended)
return;
this->wakeCPU();
DPRINTF(Quiesce, "Suspended Processor woken\n");
- this->threadContexts[0]->activate();
+ this->threadContexts[tid]->activate();
}
template <class Impl>
diff -r a8a64cca231b -r ca4ea9b5c052 src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh Wed Sep 30 11:14:19 2015 -0500
+++ b/src/cpu/o3/cpu.hh Wed Sep 30 11:14:19 2015 -0500
@@ -640,7 +640,7 @@
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
void wakeCPU();
- virtual void wakeup();
+ virtual void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
/** Gets a free thread id. Use if thread ids change across system. */
ThreadID getFreeTid();
diff -r a8a64cca231b -r ca4ea9b5c052 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/cpu/simple/atomic.cc Wed Sep 30 11:14:19 2015 -0500
@@ -140,7 +140,7 @@
for (ThreadID tid = 0; tid < numThreads; tid++) {
if (tid != sender) {
if(getCpuAddrMonitor(tid)->doMonitor(pkt)) {
- wakeup();
+ wakeup(tid);
}
TheISA::handleLockedSnoop(threadInfo[tid]->thread,
@@ -287,7 +287,7 @@
for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
- cpu->wakeup();
+ cpu->wakeup(tid);
}
}
@@ -313,7 +313,7 @@
AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
- cpu->wakeup();
+ cpu->wakeup(tid);
}
}
diff -r a8a64cca231b -r ca4ea9b5c052 src/cpu/simple/base.cc
--- a/src/cpu/simple/base.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/cpu/simple/base.cc Wed Sep 30 11:14:19 2015 -0500
@@ -416,14 +416,13 @@
}
void
-BaseSimpleCPU::wakeup()
+BaseSimpleCPU::wakeup(ThreadID tid)
{
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- getCpuAddrMonitor(tid)->gotWakeup = true;
- if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
- DPRINTF(Quiesce,"Suspended Processor awoke\n");
- threadInfo[tid]->thread->activate();
- }
+ getCpuAddrMonitor(tid)->gotWakeup = true;
+
+ if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
+ DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
+ threadInfo[tid]->thread->activate();
}
}
diff -r a8a64cca231b -r ca4ea9b5c052 src/cpu/simple/base.hh
--- a/src/cpu/simple/base.hh Wed Sep 30 11:14:19 2015 -0500
+++ b/src/cpu/simple/base.hh Wed Sep 30 11:14:19 2015 -0500
@@ -93,7 +93,7 @@
public:
BaseSimpleCPU(BaseSimpleCPUParams *params);
virtual ~BaseSimpleCPU();
- void wakeup();
+ void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
virtual void init();
public:
Trace::InstRecord *traceData;
diff -r a8a64cca231b -r ca4ea9b5c052 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/cpu/simple/timing.cc Wed Sep 30 11:14:19 2015 -0500
@@ -545,7 +545,7 @@
for (ThreadID tid = 0; tid < numThreads; tid++) {
if (tid != sender) {
if(getCpuAddrMonitor(tid)->doMonitor(pkt)) {
- wakeup();
+ wakeup(tid);
}
TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt,
dcachePort.cacheBlockMask);
@@ -865,7 +865,7 @@
{
for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
- cpu->wakeup();
+ cpu->wakeup(tid);
}
}
@@ -879,7 +879,7 @@
{
for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
- cpu->wakeup();
+ cpu->wakeup(tid);
}
}
}
diff -r a8a64cca231b -r ca4ea9b5c052 src/mem/abstract_mem.cc
--- a/src/mem/abstract_mem.cc Wed Sep 30 11:14:19 2015 -0500
+++ b/src/mem/abstract_mem.cc Wed Sep 30 11:14:19 2015 -0500
@@ -274,7 +274,8 @@
// architecture specifies that an event is
// automatically generated when clearing the exclusive
// monitor to wake up the processor in WFE.
-
system()->getThreadContext(i->contextId)->getCpuPtr()->wakeup();
+ ThreadContext* ctx = system()->getThreadContext(i->contextId);
+ ctx->getCpuPtr()->wakeup(ctx->threadId());
i = lockedAddrList.erase(i);
} else {
i++;
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