[gem5-dev] changeset in gem5: arm: Change TLB Software Caching

[Mitch Hayenga]

changeset 11da02681277 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=11da02681277
description:
        arm: Change TLB Software Caching

        In ARM, certain variables are only updated when a necessary change is
        detected.  Having 2 SMT threads share a TLB resulted in these not being
        updated as required.  This patch adds a thread context identifer to
        assist in the invalidation of these variables.

diffstat:

 src/arch/arm/tlb.cc |  6 ++++--
 src/arch/arm/tlb.hh |  1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diffs (41 lines):

diff -r ca4ea9b5c052 -r 11da02681277 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc       Wed Sep 30 11:14:19 2015 -0500
+++ b/src/arch/arm/tlb.cc       Wed Sep 30 11:14:19 2015 -0500
@@ -78,7 +78,7 @@
       stage2Mmu(NULL), rangeMRU(1),
       aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
       isHyp(false), asid(0), vmid(0), dacr(0),
-      miscRegValid(false), curTranType(NormalTran)
+      miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
 {
     tableWalker->setTlb(this);
 
@@ -1204,7 +1204,8 @@
     // check if the regs have changed, or the translation mode is different.
     // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle
     // one type of translation anyway
-    if (miscRegValid && ((tranType == curTranType) || isStage2)) {
+    if (miscRegValid && miscRegContext == tc->contextId() &&
+            ((tranType == curTranType) || isStage2)) {
         return;
     }
 
@@ -1300,6 +1301,7 @@
         }
     }
     miscRegValid = true;
+    miscRegContext = tc->contextId();
     curTranType  = tranType;
 }
 
diff -r ca4ea9b5c052 -r 11da02681277 src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh       Wed Sep 30 11:14:19 2015 -0500
+++ b/src/arch/arm/tlb.hh       Wed Sep 30 11:14:19 2015 -0500
@@ -327,6 +327,7 @@
     HCR hcr;
     uint32_t dacr;
     bool miscRegValid;
+    ContextID miscRegContext;
     ArmTranslationType curTranType;
 
     // Cached copies of system-level properties
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