changeset f98eb2da15a4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f98eb2da15a4
description:
misc: Remove redundant compiler-specific defines
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
diffstat:
src/arch/alpha/isa.hh | 4 +-
src/arch/alpha/kernel_stats.hh | 4 +-
src/arch/alpha/pagetable.hh | 4 +-
src/arch/alpha/process.hh | 2 +-
src/arch/alpha/system.hh | 4 +-
src/arch/alpha/tlb.hh | 4 +-
src/arch/arm/isa_device.hh | 4 +-
src/arch/arm/kvm/armv8_cpu.hh | 6 +-
src/arch/arm/kvm/base_cpu.hh | 4 +-
src/arch/arm/kvm/gic.hh | 20 +++---
src/arch/arm/pagetable.hh | 4 +-
src/arch/arm/pmu.hh | 16 ++--
src/arch/arm/table_walker.hh | 4 +-
src/arch/arm/tlb.hh | 8 +-
src/arch/arm/types.hh | 9 +-
src/arch/generic/types.hh | 16 ++--
src/arch/mips/interrupts.hh | 4 +-
src/arch/mips/tlb.hh | 4 +-
src/arch/power/tlb.hh | 4 +-
src/arch/power/types.hh | 5 +-
src/arch/sparc/interrupts.hh | 4 +-
src/arch/sparc/isa.hh | 4 +-
src/arch/sparc/system.hh | 4 +-
src/arch/sparc/tlb.hh | 4 +-
src/arch/x86/decoder.hh | 5 +-
src/arch/x86/interrupts.hh | 4 +-
src/arch/x86/isa.hh | 4 +-
src/arch/x86/pagetable.hh | 4 +-
src/arch/x86/regs/msr.hh | 5 +-
src/arch/x86/tlb.hh | 4 +-
src/arch/x86/types.hh | 5 +-
src/arch/x86/utility.hh | 1 -
src/base/compiler.hh | 29 ----------
src/base/cp_annotate.hh | 20 +++---
src/base/framebuffer.hh | 4 +-
src/base/hashmap.hh | 71 -------------------------
src/base/inifile.hh | 7 +-
src/base/pollevent.hh | 4 +-
src/base/random.hh | 4 +-
src/base/trace.hh | 4 +-
src/base/vnc/vncserver.hh | 4 +-
src/cpu/base.hh | 6 +-
src/cpu/checker/cpu.hh | 6 +-
src/cpu/decode_cache.hh | 9 +-
src/cpu/inst_pb_trace.hh | 4 +-
src/cpu/kvm/base.hh | 12 +--
src/cpu/kvm/x86_cpu.hh | 2 +-
src/cpu/minor/cpu.hh | 11 +--
src/cpu/minor/pipeline.hh | 2 +-
src/cpu/o3/cpu.hh | 11 +--
src/cpu/o3/lsq_unit.hh | 1 -
src/cpu/o3/mem_dep_unit.hh | 4 +-
src/cpu/o3/thread_state.hh | 4 +-
src/cpu/pred/bpred_unit.hh | 2 +-
src/cpu/simple/atomic.hh | 4 +-
src/cpu/simple/base.hh | 7 +-
src/cpu/simple/exec_context.hh | 74 ++++++++++++--------------
src/cpu/simple/probes/simpoint.hh | 9 +-
src/cpu/simple/timing.hh | 4 +-
src/cpu/simple_thread.hh | 4 +-
src/cpu/testers/rubytest/CheckTable.cc | 2 +-
src/cpu/testers/rubytest/CheckTable.hh | 4 +-
src/cpu/testers/traffic_gen/traffic_gen.hh | 11 ++-
src/cpu/thread_state.hh | 4 +-
src/dev/alpha/backdoor.hh | 8 +-
src/dev/alpha/tsunami.hh | 4 +-
src/dev/alpha/tsunami_cchip.hh | 4 +-
src/dev/alpha/tsunami_io.hh | 4 +-
src/dev/alpha/tsunami_pchip.hh | 4 +-
src/dev/arm/energy_ctrl.hh | 4 +-
src/dev/arm/flash_device.hh | 6 +-
src/dev/arm/generic_timer.hh | 26 ++++----
src/dev/arm/gic_pl390.hh | 4 +-
src/dev/arm/gpu_nomali.hh | 10 +-
src/dev/arm/hdlcd.hh | 32 +++++-----
src/dev/arm/kmi.hh | 4 +-
src/dev/arm/pl011.hh | 10 +-
src/dev/arm/pl111.hh | 4 +-
src/dev/arm/rtc_pl031.hh | 4 +-
src/dev/arm/rv_ctrl.hh | 18 +++---
src/dev/arm/timer_cpulocal.hh | 8 +-
src/dev/arm/timer_sp804.hh | 8 +-
src/dev/arm/ufs_device.hh | 6 +-
src/dev/arm/vgic.hh | 8 +-
src/dev/copy_engine.hh | 12 ++--
src/dev/copy_engine_defs.hh | 8 +-
src/dev/disk_image.hh | 8 +-
src/dev/dma_device.hh | 8 +-
src/dev/etherlink.hh | 4 +-
src/dev/ethertap.hh | 4 +-
src/dev/i2cbus.hh | 4 +-
src/dev/i8254xGBe.hh | 20 +++---
src/dev/i8254xGBe_defs.hh | 4 +-
src/dev/ide_ctrl.hh | 4 +-
src/dev/ide_disk.hh | 4 +-
src/dev/mips/malta.hh | 4 +-
src/dev/mips/malta_cchip.hh | 4 +-
src/dev/mips/malta_io.hh | 4 +-
src/dev/mips/malta_pchip.hh | 4 +-
src/dev/multi_etherlink.hh | 12 ++--
src/dev/multi_iface.hh | 4 +-
src/dev/ns_gige.hh | 6 +-
src/dev/pcidev.hh | 4 +-
src/dev/pixelpump.hh | 20 +++---
src/dev/sinic.hh | 10 +-
src/dev/sparc/dtod.hh | 4 +-
src/dev/sparc/iob.hh | 4 +-
src/dev/sparc/mm_disk.hh | 2 +-
src/dev/tcp_iface.hh | 9 +-
src/dev/uart8250.hh | 4 +-
src/dev/virtio/base.hh | 8 +-
src/dev/virtio/fs9p.hh | 4 +-
src/dev/x86/cmos.hh | 4 +-
src/dev/x86/i8042.hh | 10 +--
src/dev/x86/i82094aa.hh | 6 +-
src/dev/x86/i8237.hh | 4 +-
src/dev/x86/i8254.hh | 4 +-
src/dev/x86/i8259.hh | 4 +-
src/dev/x86/speaker.hh | 4 +-
src/kern/kernel_stats.hh | 4 +-
src/mem/cache/cache.hh | 8 +-
src/mem/cache/mshr_queue.hh | 2 +-
src/mem/cache/prefetch/stride.hh | 5 +-
src/mem/cache/tags/base_set_assoc.hh | 2 +-
src/mem/cache/tags/fa_lru.hh | 6 +-
src/mem/coherent_xbar.hh | 2 +-
src/mem/comm_monitor.hh | 12 ++--
src/mem/dram_ctrl.hh | 8 +-
src/mem/dramsim2.hh | 8 +-
src/mem/mem_checker.hh | 6 +-
src/mem/multi_level_page_table.hh | 4 +-
src/mem/packet_queue.hh | 2 +-
src/mem/page_table.hh | 8 +-
src/mem/physical.hh | 4 +-
src/mem/probes/base.hh | 4 +-
src/mem/probes/mem_trace.hh | 3 +-
src/mem/probes/stack_dist.hh | 5 +-
src/mem/ruby/common/Address.hh | 1 -
src/mem/ruby/profiler/AddressProfiler.hh | 4 +-
src/mem/ruby/profiler/Profiler.hh | 1 -
src/mem/ruby/structures/CacheMemory.cc | 4 +-
src/mem/ruby/structures/CacheMemory.hh | 4 +-
src/mem/ruby/structures/PerfectCacheMemory.hh | 5 +-
src/mem/ruby/structures/PersistentTable.hh | 4 +-
src/mem/ruby/structures/RubyMemoryControl.hh | 2 +-
src/mem/ruby/structures/TBETable.hh | 4 +-
src/mem/ruby/system/CacheRecorder.hh | 1 -
src/mem/ruby/system/DMASequencer.hh | 2 +-
src/mem/ruby/system/RubyPort.hh | 2 +-
src/mem/ruby/system/RubySystem.hh | 6 +-
src/mem/ruby/system/Sequencer.cc | 6 +-
src/mem/ruby/system/Sequencer.hh | 4 +-
src/mem/simple_mem.hh | 2 +-
src/mem/snoop_filter.hh | 4 +-
src/mem/xbar.hh | 6 +-
src/sim/clock_domain.hh | 4 +-
src/sim/dvfs_handler.hh | 4 +-
src/sim/eventq.cc | 4 +-
src/sim/eventq.hh | 4 +-
src/sim/fd_entry.hh | 4 +-
src/sim/process.hh | 6 +-
src/sim/root.hh | 6 +-
src/sim/serialize.cc | 4 +-
src/sim/sim_events.hh | 4 +-
src/sim/sim_object.hh | 6 +-
src/sim/system.hh | 6 +-
src/sim/ticked_object.hh | 8 +-
src/sim/voltage_domain.hh | 4 +-
168 files changed, 512 insertions(+), 628 deletions(-)
diffs (truncated from 3903 to 300 lines):
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/alpha/isa.hh
--- a/src/arch/alpha/isa.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/alpha/isa.hh Mon Oct 12 04:07:59 2015 -0400
@@ -92,8 +92,8 @@
memset(ipr, 0, sizeof(ipr));
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
int
flattenIntIndex(int reg) const
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/alpha/kernel_stats.hh
--- a/src/arch/alpha/kernel_stats.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/alpha/kernel_stats.hh Mon Oct 12 04:07:59 2015 -0400
@@ -86,8 +86,8 @@
void setIdleProcess(Addr idle, ThreadContext *tc);
public:
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace Kernel
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/alpha/pagetable.hh
--- a/src/arch/alpha/pagetable.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/alpha/pagetable.hh Mon Oct 12 04:07:59 2015 -0400
@@ -142,8 +142,8 @@
return ppn << PageShift;
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace AlphaISA
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/alpha/process.hh
--- a/src/arch/alpha/process.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/alpha/process.hh Mon Oct 12 04:07:59 2015 -0400
@@ -42,7 +42,7 @@
protected:
AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile);
- void loadState(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void loadState(CheckpointIn &cp) override;
void initState();
void argsInit(int intSize, int pageSize);
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/alpha/system.hh
--- a/src/arch/alpha/system.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/alpha/system.hh Mon Oct 12 04:07:59 2015 -0400
@@ -60,8 +60,8 @@
/**
* Serialization stuff
*/
- void serializeSymtab(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserializeSymtab(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serializeSymtab(CheckpointOut &cp) const override;
+ void unserializeSymtab(CheckpointIn &cp) override;
/** Override startup() to provide a path to call setupFuncEvents()
*/
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/alpha/tlb.hh Mon Oct 12 04:07:59 2015 -0400
@@ -117,8 +117,8 @@
static Fault checkCacheability(RequestPtr &req, bool itb = false);
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
// Most recently used page table entries
TlbEntry *EntryCache[3];
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/arm/isa_device.hh
--- a/src/arch/arm/isa_device.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/arm/isa_device.hh Mon Oct 12 04:07:59 2015 -0400
@@ -97,8 +97,8 @@
: BaseISADevice() {}
~DummyISADevice() {}
- void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE;
- MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE;
+ void setMiscReg(int misc_reg, MiscReg val) override;
+ MiscReg readMiscReg(int misc_reg) override;
};
}
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/arm/kvm/armv8_cpu.hh
--- a/src/arch/arm/kvm/armv8_cpu.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/arm/kvm/armv8_cpu.hh Mon Oct 12 04:07:59 2015 -0400
@@ -83,11 +83,11 @@
ArmV8KvmCPU(ArmV8KvmCPUParams *params);
virtual ~ArmV8KvmCPU();
- void dump() M5_ATTR_OVERRIDE;
+ void dump() override;
protected:
- void updateKvmState() M5_ATTR_OVERRIDE;
- void updateThreadContext() M5_ATTR_OVERRIDE;
+ void updateKvmState() override;
+ void updateThreadContext() override;
protected:
/** Mapping between integer registers in gem5 and KVM */
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/arm/kvm/base_cpu.hh
--- a/src/arch/arm/kvm/base_cpu.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/arm/kvm/base_cpu.hh Mon Oct 12 04:07:59 2015 -0400
@@ -52,10 +52,10 @@
BaseArmKvmCPU(BaseArmKvmCPUParams *params);
virtual ~BaseArmKvmCPU();
- void startup() M5_ATTR_OVERRIDE;
+ void startup() override;
protected:
- Tick kvmRun(Tick ticks) M5_ATTR_OVERRIDE;
+ Tick kvmRun(Tick ticks) override;
/** Cached state of the IRQ line */
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/arm/kvm/gic.hh
--- a/src/arch/arm/kvm/gic.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/arm/kvm/gic.hh Mon Oct 12 04:07:59 2015 -0400
@@ -76,23 +76,23 @@
KvmGic(const KvmGicParams *p);
~KvmGic();
- void startup() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
- void drainResume() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
+ void startup() override { verifyMemoryMode(); }
+ void drainResume() override { verifyMemoryMode(); }
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(Checkpoint *cp, const std::string &sec) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(Checkpoint *cp, const std::string &sec) override;
public: // PioDevice
AddrRangeList getAddrRanges() const { return addrRanges; }
- Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
- Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
public: // BaseGic
- void sendInt(uint32_t num) M5_ATTR_OVERRIDE;
- void clearInt(uint32_t num) M5_ATTR_OVERRIDE;
+ void sendInt(uint32_t num) override;
+ void clearInt(uint32_t num) override;
- void sendPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
- void clearPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
+ void sendPPInt(uint32_t num, uint32_t cpu) override;
+ void clearPPInt(uint32_t num, uint32_t cpu) override;
protected:
/**
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/arm/pagetable.hh
--- a/src/arch/arm/pagetable.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/arm/pagetable.hh Mon Oct 12 04:07:59 2015 -0400
@@ -284,7 +284,7 @@
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
SERIALIZE_SCALAR(longDescFormat);
SERIALIZE_SCALAR(pfn);
@@ -314,7 +314,7 @@
paramOut(cp, "domain", domain_);
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_SCALAR(longDescFormat);
UNSERIALIZE_SCALAR(pfn);
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/arm/pmu.hh
--- a/src/arch/arm/pmu.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/arm/pmu.hh Mon Oct 12 04:07:59 2015 -0400
@@ -96,10 +96,10 @@
void addEventProbe(unsigned int id, SimObject *obj, const char *name);
public: // SimObject and related interfaces
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
- void drainResume() M5_ATTR_OVERRIDE;
+ void drainResume() override;
public: // ISA Device interface
@@ -109,14 +109,14 @@
* @param misc_reg Register number (see miscregs.hh)
* @param val Value to store
*/
- void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE;
+ void setMiscReg(int misc_reg, MiscReg val) override;
/**
* Read a register within the PMU.
*
* @param misc_reg Register number (see miscregs.hh)
* @return Register value.
*/
- MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE;
+ MiscReg readMiscReg(int misc_reg) override;
protected: // PMU register types and constants
BitUnion32(PMCR_t)
@@ -269,7 +269,7 @@
: ProbeListenerArgBase(pm, name),
pmu(_pmu), id(_id) {}
- void notify(const uint64_t &val) M5_ATTR_OVERRIDE
+ void notify(const uint64_t &val) override
{
pmu.handleEvent(id, val);
}
@@ -329,8 +329,8 @@
listeners.reserve(4);
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/**
* Add an event count to the counter and check for overflow.
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/arm/table_walker.hh
--- a/src/arch/arm/table_walker.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/arm/table_walker.hh Mon Oct 12 04:07:59 2015 -0400
@@ -891,8 +891,8 @@
bool haveLargeAsid64() const { return _haveLargeAsid64; }
/** Checks if all state is cleared and if so, completes drain */
void completeDrain();
- DrainState drain() M5_ATTR_OVERRIDE;
- virtual void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ virtual void drainResume() override;
virtual BaseMasterPort& getMasterPort(const std::string &if_name,
PortID idx = InvalidPortID);
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/arm/tlb.hh Mon Oct 12 04:07:59 2015 -0400
@@ -284,15 +284,15 @@
bool callFromS2);
Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
- void drainResume() M5_ATTR_OVERRIDE;
+ void drainResume() override;
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void regStats();
- void regProbePoints() M5_ATTR_OVERRIDE;
+ void regProbePoints() override;
/**
* Get the table walker master port. This is used for migrating
diff -r 207d6f2f1d53 -r f98eb2da15a4 src/arch/arm/types.hh
--- a/src/arch/arm/types.hh Sat Oct 10 16:45:41 2015 -0500
+++ b/src/arch/arm/types.hh Mon Oct 12 04:07:59 2015 -0400
@@ -45,7 +45,6 @@
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
-#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "debug/Decoder.hh"
@@ -483,7 +482,7 @@
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(flags);
@@ -494,7 +493,7 @@
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