changeset 44b5c183c3cd in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=44b5c183c3cd
description:
misc: Add explicit overrides and fix other clang >= 3.5 issues
This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.
As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
diffstat:
src/arch/alpha/process.hh | 9 +-
src/arch/alpha/system.hh | 6 +-
src/arch/alpha/tlb.hh | 8 +-
src/arch/arm/table_walker.hh | 10 +-
src/arch/arm/tlb.hh | 14 +-
src/arch/generic/tlb.hh | 2 +-
src/cpu/base.hh | 8 +-
src/cpu/checker/cpu.hh | 83 +++++++-----
src/cpu/minor/cpu.hh | 28 ++--
src/cpu/minor/func_unit.cc | 2 +-
src/cpu/minor/pipeline.hh | 2 +-
src/cpu/o3/cpu.hh | 34 ++---
src/cpu/pred/bpred_unit.hh | 2 +-
src/cpu/simple/atomic.hh | 23 +-
src/cpu/simple/base.hh | 14 +-
src/cpu/simple/timing.hh | 21 +-
src/cpu/testers/traffic_gen/traffic_gen.hh | 10 +-
src/dev/alpha/backdoor.hh | 6 +-
src/dev/alpha/tsunami.hh | 18 +-
src/dev/alpha/tsunami_cchip.hh | 4 +-
src/dev/alpha/tsunami_io.hh | 6 +-
src/dev/alpha/tsunami_pchip.hh | 4 +-
src/dev/copy_engine.hh | 10 +-
src/dev/disk_image.hh | 6 +-
src/dev/dma_device.hh | 10 +-
src/dev/etherlink.hh | 2 +-
src/dev/ethertap.hh | 2 +-
src/dev/i2cbus.hh | 4 +-
src/dev/i8254xGBe.hh | 44 +++---
src/dev/ide_ctrl.hh | 8 +-
src/dev/ide_disk.hh | 2 +-
src/dev/ns_gige.hh | 8 +-
src/dev/pcidev.hh | 12 +-
src/dev/sinic.hh | 10 +-
src/dev/uart8250.hh | 8 +-
src/dev/virtio/fs9p.hh | 3 +-
src/mem/abstract_mem.hh | 4 +-
src/mem/cache/cache.hh | 12 +-
src/mem/cache/tags/base_set_assoc.hh | 32 ++--
src/mem/cache/tags/fa_lru.hh | 26 ++--
src/mem/dram_ctrl.hh | 4 +-
src/mem/dramsim2.hh | 6 +-
src/mem/page_table.hh | 12 +-
src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py | 2 -
src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh | 1 -
src/mem/ruby/structures/RubyMemoryControl.hh | 10 +-
src/mem/ruby/system/DMASequencer.hh | 4 +-
src/mem/ruby/system/RubyPort.hh | 6 +-
src/mem/ruby/system/RubySystem.hh | 8 +-
src/mem/simple_mem.hh | 4 +-
src/sim/clock_domain.hh | 2 +-
src/sim/process.hh | 4 +-
src/sim/root.hh | 2 +-
src/sim/sim_events.hh | 10 +-
src/sim/system.hh | 12 +-
src/sim/ticked_object.hh | 2 +-
src/sim/voltage_domain.hh | 4 +-
58 files changed, 307 insertions(+), 305 deletions(-)
diffs (truncated from 2028 to 300 lines):
diff -r f98eb2da15a4 -r 44b5c183c3cd src/arch/alpha/process.hh
--- a/src/arch/alpha/process.hh Mon Oct 12 04:07:59 2015 -0400
+++ b/src/arch/alpha/process.hh Mon Oct 12 04:08:01 2015 -0400
@@ -43,16 +43,17 @@
AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile);
void loadState(CheckpointIn &cp) override;
- void initState();
+ void initState() override;
void argsInit(int intSize, int pageSize);
public:
- AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
+ AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override;
/// Explicitly import the otherwise hidden getSyscallArg
using LiveProcess::getSyscallArg;
- void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val);
- void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
+ void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val)
override;
+ void setSyscallReturn(ThreadContext *tc,
+ SyscallReturn return_value) override;
};
/* No architectural page table defined for this ISA */
diff -r f98eb2da15a4 -r 44b5c183c3cd src/arch/alpha/system.hh
--- a/src/arch/alpha/system.hh Mon Oct 12 04:07:59 2015 -0400
+++ b/src/arch/alpha/system.hh Mon Oct 12 04:08:01 2015 -0400
@@ -55,7 +55,7 @@
/**
* Initialise the state of the system.
*/
- virtual void initState();
+ void initState() override;
/**
* Serialization stuff
@@ -65,7 +65,7 @@
/** Override startup() to provide a path to call setupFuncEvents()
*/
- virtual void startup();
+ void startup() override;
/**
* Set the m5AlphaAccess pointer in the console
@@ -121,7 +121,7 @@
return addFuncEvent<T>(consoleSymtab, lbl);
}
- virtual Addr fixFuncEventAddr(Addr addr);
+ Addr fixFuncEventAddr(Addr addr) override;
public:
void setIntrFreq(Tick freq) { intrFreq = freq; }
diff -r f98eb2da15a4 -r 44b5c183c3cd src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Mon Oct 12 04:07:59 2015 -0400
+++ b/src/arch/alpha/tlb.hh Mon Oct 12 04:08:01 2015 -0400
@@ -85,21 +85,21 @@
TLB(const Params *p);
virtual ~TLB();
- void takeOverFrom(BaseTLB *otlb) {}
+ void takeOverFrom(BaseTLB *otlb) override {}
- virtual void regStats();
+ void regStats() override;
int getsize() const { return table.size(); }
TlbEntry &index(bool advance = true);
void insert(Addr vaddr, TlbEntry &entry);
- void flushAll();
+ void flushAll() override;
void flushProcesses();
void flushAddr(Addr addr, uint8_t asn);
void
- demapPage(Addr vaddr, uint64_t asn)
+ demapPage(Addr vaddr, uint64_t asn) override
{
assert(asn < (1 << 8));
flushAddr(vaddr, asn);
diff -r f98eb2da15a4 -r 44b5c183c3cd src/arch/arm/table_walker.hh
--- a/src/arch/arm/table_walker.hh Mon Oct 12 04:07:59 2015 -0400
+++ b/src/arch/arm/table_walker.hh Mon Oct 12 04:08:01 2015 -0400
@@ -884,7 +884,7 @@
return dynamic_cast<const Params *>(_params);
}
- virtual void init();
+ void init() override;
bool haveLPAE() const { return _haveLPAE; }
bool haveVirtualization() const { return _haveVirtualization; }
@@ -892,12 +892,12 @@
/** Checks if all state is cleared and if so, completes drain */
void completeDrain();
DrainState drain() override;
- virtual void drainResume() override;
+ void drainResume() override;
- virtual BaseMasterPort& getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ BaseMasterPort& getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID) override;
- void regStats();
+ void regStats() override;
Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid,
bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
diff -r f98eb2da15a4 -r 44b5c183c3cd src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh Mon Oct 12 04:07:59 2015 -0400
+++ b/src/arch/arm/tlb.hh Mon Oct 12 04:08:01 2015 -0400
@@ -155,10 +155,10 @@
virtual ~TLB();
- void takeOverFrom(BaseTLB *otlb);
+ void takeOverFrom(BaseTLB *otlb) override;
/// setup all the back pointers
- virtual void init();
+ void init() override;
TableWalker *getTableWalker() { return tableWalker; }
@@ -197,7 +197,7 @@
/** Reset the entire TLB. Used for CPU switching to prevent stale
* translations after multiple switches
*/
- void flushAll()
+ void flushAll() override
{
flushAllSecurity(false, 0, true);
flushAllSecurity(true, 0, true);
@@ -230,14 +230,12 @@
void printTlb() const;
- void demapPage(Addr vaddr, uint64_t asn)
+ void demapPage(Addr vaddr, uint64_t asn) override
{
// needed for x86 only
panic("demapPage() is not implemented.\n");
}
- static bool validVirtualAddress(Addr vaddr);
-
/**
* Do a functional lookup on the TLB (for debugging)
* and don't modify any internal state
@@ -290,7 +288,7 @@
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
- void regStats();
+ void regStats() override;
void regProbePoints() override;
@@ -304,7 +302,7 @@
*
* @return A pointer to the walker master port
*/
- virtual BaseMasterPort* getMasterPort();
+ BaseMasterPort* getMasterPort() override;
// Caching misc register values here.
// Writing to misc registers needs to invalidate them.
diff -r f98eb2da15a4 -r 44b5c183c3cd src/arch/generic/tlb.hh
--- a/src/arch/generic/tlb.hh Mon Oct 12 04:07:59 2015 -0400
+++ b/src/arch/generic/tlb.hh Mon Oct 12 04:08:01 2015 -0400
@@ -123,7 +123,7 @@
{}
public:
- void demapPage(Addr vaddr, uint64_t asn);
+ void demapPage(Addr vaddr, uint64_t asn) override;
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
diff -r f98eb2da15a4 -r 44b5c183c3cd src/cpu/base.hh
--- a/src/cpu/base.hh Mon Oct 12 04:07:59 2015 -0400
+++ b/src/cpu/base.hh Mon Oct 12 04:08:01 2015 -0400
@@ -189,7 +189,7 @@
* @return a reference to the port with the given name
*/
BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ PortID idx = InvalidPortID) override;
/** Get cpu task id */
uint32_t taskId() const { return _taskId; }
@@ -303,9 +303,9 @@
BaseCPU(Params *params, bool is_checker = false);
virtual ~BaseCPU();
- virtual void init();
- virtual void startup();
- virtual void regStats();
+ void init() override;
+ void startup() override;
+ void regStats() override;
void regProbePoints() override;
diff -r f98eb2da15a4 -r 44b5c183c3cd src/cpu/checker/cpu.hh
--- a/src/cpu/checker/cpu.hh Mon Oct 12 04:07:59 2015 -0400
+++ b/src/cpu/checker/cpu.hh Mon Oct 12 04:08:01 2015 -0400
@@ -98,7 +98,7 @@
/** id attached to all issued requests */
MasterID masterId;
public:
- virtual void init();
+ void init() override;
typedef CheckerCPUParams Params;
CheckerCPU(Params *p);
@@ -110,7 +110,7 @@
void setDcachePort(MasterPort *dcache_port);
- MasterPort &getDataPort()
+ MasterPort &getDataPort() override
{
// the checker does not have ports on its own so return the
// data port of the actual CPU core
@@ -118,7 +118,7 @@
return *dcachePort;
}
- MasterPort &getInstPort()
+ MasterPort &getInstPort() override
{
// the checker does not have ports on its own so return the
// data port of the actual CPU core
@@ -175,12 +175,12 @@
TheISA::TLB* getITBPtr() { return itb; }
TheISA::TLB* getDTBPtr() { return dtb; }
- virtual Counter totalInsts() const
+ virtual Counter totalInsts() const override
{
return 0;
}
- virtual Counter totalOps() const
+ virtual Counter totalOps() const override
{
return 0;
}
@@ -194,8 +194,10 @@
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
- void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
- Addr getEA() const { panic("SimpleCPU::getEA() not implemented\n"); }
+ void setEA(Addr EA) override
+ { panic("CheckerCPU::setEA() not implemented\n"); }
+ Addr getEA() const override
+ { panic("CheckerCPU::getEA() not implemented\n"); }
// The register accessor methods provide the index of the
// instruction's operand (e.g., 0 or 1), not the architectural
@@ -208,24 +210,25 @@
// storage (which is pretty hard to imagine they would have reason
// to do).
- IntReg readIntRegOperand(const StaticInst *si, int idx)
+ IntReg readIntRegOperand(const StaticInst *si, int idx) override
{
return thread->readIntReg(si->srcRegIdx(idx));
}
- FloatReg readFloatRegOperand(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
return thread->readFloatReg(reg_idx);
}
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si,
+ int idx) override
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
return thread->readFloatRegBits(reg_idx);
}
- CCReg readCCRegOperand(const StaticInst *si, int idx)
+ CCReg readCCRegOperand(const StaticInst *si, int idx) override
{
int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
return thread->readCCReg(reg_idx);
@@ -239,13 +242,15 @@
result.push(instRes);
}
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
