> On Nov. 4, 2015, 5:37 a.m., Steve Reinhardt wrote:
> > src/dev/io_device.cc, line 59
> > <http://reviews.gem5.org/r/3172/diff/1/?file=50905#file50905line59>
> >
> >     minor, but 'additional_latency' is rather nondescript. maybe 
> > 'transmission_delay' or 'receive_delay' or 'receive_latency' or something 
> > like thet?

It is headerDelay (pipeline delay) and payloadDelay (de-serialisation delay). I 
am happy to change, but I don't think there is a short and snappy word 
describing it.


- Andreas


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On Oct. 30, 2015, 10:35 a.m., Andreas Hansson wrote:
> 
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3172/
> -----------------------------------------------------------
> 
> (Updated Oct. 30, 2015, 10:35 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> -------
> 
> Changeset 11188:353cf88682b9
> ---------------------------
> mem: Use the packet delays and do not just zero them out
> 
> This patch updates the I/O devices, bridge and simple memory to take
> the packet header and payload delay into account in their latency
> calculations. In all cases we add the header delay, i.e. the
> accumulated pipeline delay of any crossbars, and the payload delay
> needed for deserialisation of any payload.
> 
> Due to the additional unknown latency contribution, the packet queue
> of the simple memory is changed to use insertion sorting based on the
> time stamp. Moreover, since the memory hands out exclusive (non
> shared) responses, we also need to ensure ordering for reads to the
> same address.
> 
> 
> Diffs
> -----
> 
>   src/dev/io_device.cc 4daf60db14d7 
>   src/dev/pcidev.cc 4daf60db14d7 
>   src/mem/bridge.cc 4daf60db14d7 
>   src/mem/simple_mem.hh 4daf60db14d7 
>   src/mem/simple_mem.cc 4daf60db14d7 
> 
> Diff: http://reviews.gem5.org/r/3172/diff/
> 
> 
> Testing
> -------
> 
> 
> Thanks,
> 
> Andreas Hansson
> 
>

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