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(Updated Nov. 4, 2015, 9:34 a.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 11191:d5063101794c --------------------------- mem: Use the packet delays and do not just zero them out This patch updates the I/O devices, bridge and simple memory to take the packet header and payload delay into account in their latency calculations. In all cases we add the header delay, i.e. the accumulated pipeline delay of any crossbars, and the payload delay needed for deserialisation of any payload. Due to the additional unknown latency contribution, the packet queue of the simple memory is changed to use insertion sorting based on the time stamp. Moreover, since the memory hands out exclusive (non shared) responses, we also need to ensure ordering for reads to the same address. Diffs (updated) ----- src/dev/io_device.cc 2d1d51615e0e src/dev/pcidev.cc 2d1d51615e0e src/mem/bridge.cc 2d1d51615e0e src/mem/simple_mem.hh 2d1d51615e0e src/mem/simple_mem.cc 2d1d51615e0e Diff: http://reviews.gem5.org/r/3172/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
