Hi, I am trying to implement a HTM(Hardware Transactional Memory) in Gem5 with x86. For that I want to configure a system with 4 cores, each having 2 levels of private caches and a third level of shared cache. can anyone help me out with this, because I am really new to this Gem5.
regards, Rohith _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
