Hi Rohith, The classic memory system is using a MOESI-based coherency protocol, and supports very flexible topologies built around crossbars. For anything up to 8-16 cores it is a very good starting point in my view.
For the second question the scope is truly huge. You may want to have a look at the caches, as well as the memory controller. Also, these days gem5 supports “Buffer on Board” style memory systems using an on-chip controller as well as an off-chip memory controller, so you may even consider both of these. I suspect the answer to the question “where should this functionality go” would be enough for a couple of PhD theses... Andreas On 06/11/2015, 05:07, "gem5-dev on behalf of rohith mathew" <[email protected] on behalf of [email protected]> wrote: >Hi Andreas, >Thanks for the support. I have some doubt like, > >1)if we want to use coherency protocols, is classic memory system enough >or >do we need to go for ruby? >2)If I want to occupy some database operations in main memory for my HTM >implementation, which all files I should work with? > >Thanks in advance. > >regards, >Rohith > >On Thu, Nov 5, 2015 at 2:00 PM, Andreas Hansson <[email protected]> >wrote: > >> Hi Rohith, >> >> I am afraid I cannot help you with the HTM bit (there was some previous >> work posted on the review board years ago...), but when it comes to the >> system topology, the gem5 classic memory system is very flexible. >> >> I’d suggest to write your own config script, possibly based on >> config/fs.py, or even the “learning-gem5” scripts. Simply instantiate >>the >> components, and CPU clusters one by one, connect them up, and off you >>go. >> It really is not that complex. The biggest problem here is that the >> existing example scripts try to accommodate a lot of various topologies, >> and do so by means of if-statements. >> >> Andreas >> >> On 05/11/2015, 05:59, "gem5-dev on behalf of rohith mathew" >> <[email protected] on behalf of [email protected]> wrote: >> >> >Hi, >> > >> >I am trying to implement a HTM(Hardware Transactional Memory) in Gem5 >>with >> >x86. For that I want to configure a system with 4 cores, each having 2 >> >levels of private caches and a third level of shared cache. can anyone >> >help >> >me out with this, because I am really new to this Gem5. >> > >> >regards, >> >Rohith >> >_______________________________________________ >> >gem5-dev mailing list >> >[email protected] >> >http://m5sim.org/mailman/listinfo/gem5-dev >> >> >> ________________________________ >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >> confidential and may also be privileged. If you are not the intended >> recipient, please notify the sender immediately and do not disclose the >> contents to any other person, use it for any purpose, or store or copy >>the >> information in any medium. Thank you. >> _______________________________________________ >> gem5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/gem5-dev >> >_______________________________________________ >gem5-dev mailing list >[email protected] >http://m5sim.org/mailman/listinfo/gem5-dev ________________________________ -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
