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(Updated Dec. 24, 2015, 8:59 a.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 11281:fc4962869323 --------------------------- mem: Make cache terminology easier to understand This patch changes the name of a bunch of packet flags and MSHR member functions and variables to make the coherency protocol easier to understand. In addition the patch adds and updates lots of descriptions, explicitly spelling out assumptions. The following name changes are made: * the packet memInhibit flag is renamed to cacheResponding * the packet shared flag is renamed to passNonWritable * the packet NeedsExclusive attribute is renamed to NeedsWritable * the packet isSupplyExclusive is renamed responderHadWritable * the MSHR pendingDirty is renamed to pendingWritable The cache states, Modified, Owned, Exclusive, Shared are also called out in the cache and MSHR code to make it easier to understand. Diffs (updated) ----- src/mem/cache/mshr.hh d9a0136ab8cc src/mem/cache/cache.cc d9a0136ab8cc src/mem/cache/cache.hh d9a0136ab8cc src/mem/cache/blk.hh d9a0136ab8cc src/mem/bridge.cc d9a0136ab8cc src/mem/cache/base.hh d9a0136ab8cc src/mem/addr_mapper.cc d9a0136ab8cc src/mem/dramsim2.cc d9a0136ab8cc src/mem/hmc_controller.cc d9a0136ab8cc src/mem/dram_ctrl.cc d9a0136ab8cc src/mem/comm_monitor.cc d9a0136ab8cc src/mem/coherent_xbar.cc d9a0136ab8cc src/mem/cache/mshr_queue.cc d9a0136ab8cc src/mem/cache/mshr.cc d9a0136ab8cc src/mem/cache/mshr_queue.hh d9a0136ab8cc src/mem/ruby/system/RubyPort.cc d9a0136ab8cc src/mem/ruby/system/DMASequencer.cc d9a0136ab8cc src/mem/packet.hh d9a0136ab8cc src/mem/packet.cc d9a0136ab8cc src/mem/noncoherent_xbar.cc d9a0136ab8cc src/mem/mem_checker_monitor.cc d9a0136ab8cc src/mem/snoop_filter.cc d9a0136ab8cc src/mem/tport.cc d9a0136ab8cc src/mem/simple_mem.cc d9a0136ab8cc src/mem/serial_link.cc d9a0136ab8cc src/mem/abstract_mem.cc d9a0136ab8cc src/cpu/o3/cpu.cc d9a0136ab8cc src/dev/dma_device.cc d9a0136ab8cc Diff: http://reviews.gem5.org/r/3254/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
