> On Dec. 26, 2015, 3:27 p.m., Steve Reinhardt wrote: > > src/mem/packet.hh, line 270 > > <http://reviews.gem5.org/r/3254/diff/2-3/?file=52284#file52284line270> > > > > I find the description from here on down confusing. The owner is not > > passing the block as writable, the owner is just passing the block data > > along with ownership. (How can it "pass" writability when it didn't have > > it to begin with?) The writability comes from the fact that needsWritable > > -> isInvalidate, so all other copies are also invalidated as a side effect > > of the request. > > Andreas Hansson wrote: > Note that at the moment NeedsWritable is not always equal to > IsInvalidate. They are two independent flags. > > I agree with your statement though. I'll change it to say that we respond > without removing writable, as we rely on all other copies being invalidated.
They are two independent flags, yes, but as an assertion I've seen recently claims, they are always set identically for coherent requests that get snooped :). - Steve ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3254/#review7762 ----------------------------------------------------------- On Dec. 28, 2015, 10:02 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3254/ > ----------------------------------------------------------- > > (Updated Dec. 28, 2015, 10:02 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11281:35bb7d1f0588 > --------------------------- > mem: Make cache terminology easier to understand > > This patch changes the name of a bunch of packet flags and MSHR member > functions and variables to make the coherency protocol easier to > understand. In addition the patch adds and updates lots of > descriptions, explicitly spelling out assumptions. > > The following name changes are made: > > * the packet memInhibit flag is renamed to cacheResponding > > * the packet shared flag is renamed to passNonWritable > > * the packet NeedsExclusive attribute is renamed to NeedsWritable > > * the packet isSupplyExclusive is renamed responderHadWritable > > * the MSHR pendingDirty is renamed to pendingWritable > > The cache states, Modified, Owned, Exclusive, Shared are also called > out in the cache and MSHR code to make it easier to understand. > > > Diffs > ----- > > src/mem/packet.cc 3fd1142adad9 > src/mem/ruby/system/DMASequencer.cc 3fd1142adad9 > src/mem/ruby/system/RubyPort.cc 3fd1142adad9 > src/mem/serial_link.cc 3fd1142adad9 > src/mem/simple_mem.cc 3fd1142adad9 > src/mem/snoop_filter.cc 3fd1142adad9 > src/mem/tport.cc 3fd1142adad9 > src/mem/abstract_mem.cc 3fd1142adad9 > src/mem/addr_mapper.cc 3fd1142adad9 > src/mem/bridge.cc 3fd1142adad9 > src/mem/cache/base.hh 3fd1142adad9 > src/mem/cache/blk.hh 3fd1142adad9 > src/mem/cache/cache.hh 3fd1142adad9 > src/mem/cache/cache.cc 3fd1142adad9 > src/mem/cache/mshr.hh 3fd1142adad9 > src/mem/cache/mshr.cc 3fd1142adad9 > src/mem/cache/mshr_queue.hh 3fd1142adad9 > src/mem/cache/mshr_queue.cc 3fd1142adad9 > src/mem/coherent_xbar.cc 3fd1142adad9 > src/mem/comm_monitor.cc 3fd1142adad9 > src/mem/dram_ctrl.cc 3fd1142adad9 > src/mem/dramsim2.cc 3fd1142adad9 > src/mem/hmc_controller.cc 3fd1142adad9 > src/mem/mem_checker_monitor.cc 3fd1142adad9 > src/mem/noncoherent_xbar.cc 3fd1142adad9 > src/mem/packet.hh 3fd1142adad9 > src/cpu/o3/cpu.cc 3fd1142adad9 > src/dev/dma_device.cc 3fd1142adad9 > > Diff: http://reviews.gem5.org/r/3254/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
