Independent of your CLs, I saw when implementing the SSE stuff that it's definitely designed so that it can be done in two, independent 64 bit halves, probably by two 64 bit FPUs. The only exception I remember were 128 bit shift instructions which would shift bits between the two halves. That's why I implemented things by generally just doing everything twice, once for each half of the registers. I'm not that familiar with the more recent 256 bit instructions so that may have changed. I can see why accessing the full 128 bits atomically would be helpful, though.
Gabe On Wed, Feb 3, 2016 at 2:27 PM, Steve Reinhardt <[email protected]> wrote: > I posted most of these x86 patches two weeks ago. If I don't hear > something by Friday (2/5), I'll assume that no one wants to review them, > and will commit them sometime after that. > > http://reviews.gem5.org/r/3290/ > http://reviews.gem5.org/r/3291/ > http://reviews.gem5.org/r/3307/ > > Thanks, > > Steve > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
