Thanks for the input, Gabe. I'm not surprised that SSE is designed specifically to enable a dual-pumped 64-bit implementation; whether to do it that way or to spend more resources on a single-cycle 128-bit implementation is just a design trade-off that might be made differently for different products, while maintaining binary compatibility.
I'd be surprised if that's not still true of AVX and AVX-512, that they're designed to be implemented either with full-width or half-width (or perhaps even narrower) pipelines. If we ever decided to make that configurable in gem5 it would be a pain, as it may well require having separate microcode implementations. I doubt that's an issue we'll have to face anytime soon though. Steve On Thu, Feb 4, 2016 at 3:54 PM Gabe Black <[email protected]> wrote: > Independent of your CLs, I saw when implementing the SSE stuff that it's > definitely designed so that it can be done in two, independent 64 bit > halves, probably by two 64 bit FPUs. The only exception I remember were 128 > bit shift instructions which would shift bits between the two halves. > That's why I implemented things by generally just doing everything twice, > once for each half of the registers. I'm not that familiar with the more > recent 256 bit instructions so that may have changed. I can see why > accessing the full 128 bits atomically would be helpful, though. > > Gabe > > On Wed, Feb 3, 2016 at 2:27 PM, Steve Reinhardt <[email protected]> wrote: > > > I posted most of these x86 patches two weeks ago. If I don't hear > > something by Friday (2/5), I'll assume that no one wants to review them, > > and will commit them sometime after that. > > > > http://reviews.gem5.org/r/3290/ > > http://reviews.gem5.org/r/3291/ > > http://reviews.gem5.org/r/3307/ > > > > Thanks, > > > > Steve > > _______________________________________________ > > gem5-dev mailing list > > [email protected] > > http://m5sim.org/mailman/listinfo/gem5-dev > > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
