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Ship it! Ship It! - Steve Reinhardt On Jan. 1, 2016, 6:33 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3271/ > ----------------------------------------------------------- > > (Updated Jan. 1, 2016, 6:33 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11297:bcef70bdf6e3 > --------------------------- > mem: Move the point of coherency to the coherent crossbar > > This patch introduces the ability of making the coherent crossbar the > point of coherency. If so, the crossbar does not forward packets where > a cache with ownership has already committed to responding, and also > does not forward any coherency-related packets that are not intended > for a downstream memory controller. Thus, invalidations and upgrades > are turned around in the crossbar, and the memory controller only sees > normal reads and writes. > > In addition this patch moves the express snoop promotion of a packet > to the crossbar, thus allowing the downstream cache to check the > express snoop flag (as it should) for bypassing any blocking, rather > than relying on whether a cache is responding or not. > > > Diffs > ----- > > src/mem/XBar.py 57c340f947c7 > src/mem/bridge.cc 57c340f947c7 > src/mem/cache/cache.cc 57c340f947c7 > src/mem/coherent_xbar.hh 57c340f947c7 > src/mem/coherent_xbar.cc 57c340f947c7 > src/mem/dram_ctrl.cc 57c340f947c7 > src/mem/simple_mem.cc 57c340f947c7 > configs/example/memtest.py 57c340f947c7 > > Diff: http://reviews.gem5.org/r/3271/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
