Hi,
I was trying to program gic in bare-metal mode using the following
programming sequence (copied from system/arm/aarch64_bootloader/boot.S) :-
* // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
// Test the the MPIDR_EL1 register against 0xff00ffffff to //
extract the primary CPU. ldr x1, =0xff00ffffff tst x0, x1
// check for cpuid==zero b.ne <http://b.ne> 1f
// secondary CPU ldr x1, =GIC_DIST_BASE // GICD_CTLR mov w0,
#3 // EnableGrp0 | EnableGrp1 str w0, [x1]1: ldr x1, =GIC_DIST_BASE
+ 0x80 // GICD_IGROUPR mov w0, #~0 // Grp1 interrupts str w0,
[x1], #4 b.ne <http://b.ne> 2f // Only local interrupts for
secondary CPUs str w0, [x1], #4 str w0, [x1], #42: ldr x1,
=GIC_CPU_BASE // GICC_CTLR ldr w0, [x1] mov w0, #3 //
EnableGrp0 | EnableGrp1 str w0, [x1] mov w0, #1 << 7 // allow
NS access to GICC_PMR str w0, [x1, #4] // GICC_PMR*
gem5 is throwing following error on this :-
*panic: Tried to write Gic distributor at offset 0x80*
* @ tick 9000*
*[writeDistributor:build/ARM/dev/arm/gic_pl390.cc, line 512]*
On this, I checked the source myself and found that register GICD_IGROUPR
as specified in gicv2 manual is missing. Does that mean we are missing full
support for GICv2 at this time or something ?
Please guide.
I am using latest copy of gem5-dev repository for compiling.
thanks,
vikas
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