Hi Vikas, The GIC model in gem5 is unfortunately a GICv1. It has some gem5-specific extensions to support more than 8 cores, but it doesn¹t support optional GICv1 features such as security extensions. Unfortunately, the way the GIC model handles accesses to unsupported registers, such as GICD_IGROUPn, isn¹t according to to spec. There is a good reason for this though, we normally want to detect if the simulated system is using these registers and let the user know that they aren¹t supported.
Real GICv1 hardware without security extensions implement GICD_IGROUPRn as RAZ/WI. We should probably do this as well and warn_once() if the guest accesses these registers. I won¹t have time to look into this myself anytime soon, so I¹d suggest that you prepare a patch. If you do, could you please add me as a reviewer? That ensures a quicker review cycle since the notification email will be addressed directly to me. Regards, Andreas On 01/03/2016, 19:37, "gem5-dev on behalf of vikas chauhan" <[email protected] on behalf of [email protected]> wrote: >Hi, >I was trying to program gic in bare-metal mode using the following >programming sequence (copied from system/arm/aarch64_bootloader/boot.S) :- > > > > > > > > > > > > > > > > > > > > > > > > > >* // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0 >// Test the the MPIDR_EL1 register against 0xff00ffffff to // >extract the primary CPU. ldr x1, =0xff00ffffff tst x0, x1 > // check for cpuid==zero b.ne <http://b.ne> 1f > // secondary CPU ldr x1, =GIC_DIST_BASE // GICD_CTLR mov >w0, >#3 // EnableGrp0 | EnableGrp1 str w0, [x1]1: ldr x1, =GIC_DIST_BASE >+ 0x80 // GICD_IGROUPR mov w0, #~0 // Grp1 interrupts str >w0, >[x1], #4 b.ne <http://b.ne> 2f // Only local interrupts for >secondary CPUs str w0, [x1], #4 str w0, [x1], #42: ldr x1, >=GIC_CPU_BASE // GICC_CTLR ldr w0, [x1] mov w0, #3 // >EnableGrp0 | EnableGrp1 str w0, [x1] mov w0, #1 << 7 // >allow >NS access to GICC_PMR str w0, [x1, #4] // GICC_PMR* > >gem5 is throwing following error on this :- > >*panic: Tried to write Gic distributor at offset 0x80* >* @ tick 9000* >*[writeDistributor:build/ARM/dev/arm/gic_pl390.cc, line 512]* > >On this, I checked the source myself and found that register GICD_IGROUPR >as specified in gicv2 manual is missing. Does that mean we are missing >full >support for GICv2 at this time or something ? > >Please guide. >I am using latest copy of gem5-dev repository for compiling. > >thanks, >vikas >_______________________________________________ >gem5-dev mailing list >[email protected] >http://m5sim.org/mailman/listinfo/gem5-dev IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
