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(Updated March 6, 2016, 5:38 p.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 11367:5fe50a8b3c55 --------------------------- mem: Adjust cache queue reserve to more conservative values The cache queue reserve is there as an overflow to give us enough headroom based on when we block the cache, and how many transactions we may already have accepted before actually blocking. The previous values were probably chosen to be "big enough", when we actually know that we check the MSHRs after every single allocation, and for the write buffers we know that we implicitly may need one entry for every outstanding MSHR. Diffs (updated) ----- src/mem/cache/base.cc 1bd9f1b27438 src/mem/cache/queue.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3347/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
