> On Feb. 14, 2016, 12:24 p.m., Andreas Hansson wrote: > > After pushing the patch that moves the point of coherency to the > > CoherentXBar we should probably update this to match the code in bridge.cc. > > Abdul Mutaal Ahmad wrote: > when is that patch expected to be pushed? if it is already there, can you > please share here.
It was pushed a few weeks ago and you can have a look at e.g. bridge.cc for a suitable check. In essence all coherency traffic should stop in the CoherentXBar and never reach the TLM adapter. - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3313/#review8011 ----------------------------------------------------------- On Feb. 3, 2016, 3:37 p.m., Abdul Mutaal Ahmad wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3313/ > ----------------------------------------------------------- > > (Updated Feb. 3, 2016, 3:37 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > memInhibitAsserted() has been removed from packet.hh. This change has been > reflected in TLM based SystemC memory > > > Diffs > ----- > > util/tlm/sc_port.cc UNKNOWN > > Diff: http://reviews.gem5.org/r/3313/diff/ > > > Testing > ------- > > > Thanks, > > Abdul Mutaal Ahmad > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
