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Thanks for looking into this! I'd suggest that you implement this as a GICv1 without security extensions. According to the architecture spec, the ICDISRn registers should be RAZ/WI in that case, so no need to store additional state. src/dev/arm/gic_pl390.cc (line 410) <http://reviews.gem5.org/r/3375/#comment6979> Isn't there some code missing here? - Andreas Sandberg On March 15, 2016, 4:58 p.m., Bjoern A. Zeeb wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3375/ > ----------------------------------------------------------- > > (Updated March 15, 2016, 4:58 p.m.) > > > Review request for Default and Andreas Sandberg. > > > Repository: gem5 > > > Description > ------- > > arm,dev: add (dummy) ISecR support to the PL390 GIC > > Add (dummy) support for Interrupt Security Registers to allow > software to read/write them even though we do not properly > implement checks yet. This avoids hitting panic()s and > seems to be `good enough' to get certain software running > happily. > > > Diffs > ----- > > src/dev/arm/gic_pl390.hh 2fd64ea0a7cb > src/dev/arm/gic_pl390.cc 2fd64ea0a7cb > > Diff: http://reviews.gem5.org/r/3375/diff/ > > > Testing > ------- > > > Thanks, > > Bjoern A. Zeeb > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
