> On March 15, 2016, 11:13 p.m., Andreas Sandberg wrote: > > Thanks for looking into this! > > > > I'd suggest that you implement this as a GICv1 without security extensions. > > According to the architecture spec, the ICDISRn registers should be RAZ/WI > > in that case, so no need to store additional state.
Well the problem seems to be that a pfr(1) returns with & 0x000000f0 being true, which is how FreeBSD (and probably everyone else) would detect whether SecExt are present. So I assume we should drop the bits as well from ArmISA.py id_pfr1 ( id_pfr1 = Param.UInt32(0x00001011, "Processor Feature Register 1") )? At least currently assuming they are not there is not an option. Side note: FreeBSD code doesn't all do the right thing everywhere either depending on that flag but for as long as it's there we do and gem5 doesn't. > On March 15, 2016, 11:13 p.m., Andreas Sandberg wrote: > > src/dev/arm/gic_pl390.cc, line 410 > > <http://reviews.gem5.org/r/3375/diff/1/?file=54094#file54094line410> > > > > Isn't there some code missing here? Yes I know. I had not intentions to do the 100% right thing throughout the entire ARM platform. I am just working around my problem and leaving the comment for someone to finish the work who knows better and can test better than I can ;-) - Bjoern A. ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3375/#review8090 ----------------------------------------------------------- On March 15, 2016, 4:58 p.m., Bjoern A. Zeeb wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3375/ > ----------------------------------------------------------- > > (Updated March 15, 2016, 4:58 p.m.) > > > Review request for Default and Andreas Sandberg. > > > Repository: gem5 > > > Description > ------- > > arm,dev: add (dummy) ISecR support to the PL390 GIC > > Add (dummy) support for Interrupt Security Registers to allow > software to read/write them even though we do not properly > implement checks yet. This avoids hitting panic()s and > seems to be `good enough' to get certain software running > happily. > > > Diffs > ----- > > src/dev/arm/gic_pl390.hh 2fd64ea0a7cb > src/dev/arm/gic_pl390.cc 2fd64ea0a7cb > > Diff: http://reviews.gem5.org/r/3375/diff/ > > > Testing > ------- > > > Thanks, > > Bjoern A. Zeeb > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
