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util/tlm/tlm_elastic.py (line 1) <http://reviews.gem5.org/r/3477/#comment7242> *2016. util/tlm/tlm_elastic.py (line 128) <http://reviews.gem5.org/r/3477/#comment7243> *instantiated util/tlm/tlm_elastic.py (lines 141 - 142) <http://reviews.gem5.org/r/3477/#comment7241> CPU should be connected to L1 caches instead of membus. I think it would be best to call the CacheConfig.config_caches(options, system) here to incorporate all common options related to caches. - Radhika Jagtap On May 25, 2016, 10:08 p.m., Matthias Jung wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3477/ > ----------------------------------------------------------- > > (Updated May 25, 2016, 10:08 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > This patch adds an example configuration for elastic trace playing into the > SystemC world, similar to the already existing traffic generator example in > /util/tlm. > > > Diffs > ----- > > util/tlm/README fc247b9c42b6 > util/tlm/tlm_elastic.py PRE-CREATION > > Diff: http://reviews.gem5.org/r/3477/diff/ > > > Testing > ------- > > > Thanks, > > Matthias Jung > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
