> On May 26, 2016, 10 a.m., Radhika Jagtap wrote: > > util/tlm/tlm_elastic.py, lines 141-142 > > <http://reviews.gem5.org/r/3477/diff/1/?file=55558#file55558line141> > > > > CPU should be connected to L1 caches instead of membus. I think it > > would be best to call the CacheConfig.config_caches(options, system) here > > to incorporate all common options related to caches. > > Jason Lowe-Power wrote: > I actually think it should be kept as is. The point here is to make an > example script, not necessarily a script that a user should use without > modification. Maybe just a comment that says something like "adding caches > here may be important"?
The pecularity here is that without L1 caches it is like connected the load store queue to the memory bus. Besides it's just a couple of lines that need to be changed. - Radhika ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3477/#review8341 ----------------------------------------------------------- On May 25, 2016, 10:08 p.m., Matthias Jung wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3477/ > ----------------------------------------------------------- > > (Updated May 25, 2016, 10:08 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > This patch adds an example configuration for elastic trace playing into the > SystemC world, similar to the already existing traffic generator example in > /util/tlm. > > > Diffs > ----- > > util/tlm/README fc247b9c42b6 > util/tlm/tlm_elastic.py PRE-CREATION > > Diff: http://reviews.gem5.org/r/3477/diff/ > > > Testing > ------- > > > Thanks, > > Matthias Jung > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
