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Review request for Default. Repository: gem5 Description ------- Changeset 11497:5460f7fd3c8f --------------------------- arm: Correctly check translation mode (aarch64/aarch32) According to the ARM ARM (see AArch32.TranslateAddress in the pseudocode library), the TLB should be operating in aarch64 mode if the EL0 is aarch32 and EL1 is aarch64. This is currently not the case in gem5, which breaks 64/32 interprocessing. Update the check to match the reference manual. Change-Id: I6f1444d57c0e2eb5f8880f513f33a9197b7cb2ce Signed-off-by: Andreas Sandberg <[email protected]> Reviewed-by: Mitch Hayenga <[email protected]> Reviewed-by: Nikos Nikoleris <[email protected]> Diffs ----- src/arch/arm/tlb.cc 1f04f97c014d Diff: http://reviews.gem5.org/r/3482/diff/ Testing ------- Thanks, Andreas Sandberg _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
