changeset 55256a05d9e9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=55256a05d9e9
description:
arm: Correctly check translation mode (aarch64/aarch32)
According to the ARM ARM (see AArch32.TranslateAddress in the
pseudocode library), the TLB should be operating in aarch64 mode if
the EL0 is aarch32 and EL1 is aarch64. This is currently not the case
in gem5, which breaks 64/32 interprocessing. Update the check to match
the reference manual.
Change-Id: I6f1444d57c0e2eb5f8880f513f33a9197b7cb2ce
Signed-off-by: Andreas Sandberg <[email protected]>
Reviewed-by: Mitch Hayenga <[email protected]>
Reviewed-by: Nikos Nikoleris <[email protected]>
diffstat:
src/arch/arm/tlb.cc | 12 ++++++++----
1 files changed, 8 insertions(+), 4 deletions(-)
diffs (23 lines):
diff -r f3184dd8257f -r 55256a05d9e9 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Tue May 31 11:27:00 2016 +0100
+++ b/src/arch/arm/tlb.cc Tue May 31 12:14:37 2016 +0100
@@ -1197,11 +1197,15 @@
DPRINTF(TLBVerbose, "TLB variables changed!\n");
cpsr = tc->readMiscReg(MISCREG_CPSR);
+
// Dependencies: SCR/SCR_EL3, CPSR
- isSecure = inSecureState(tc);
- isSecure &= (tranType & HypMode) == 0;
- isSecure &= (tranType & S1S2NsTran) == 0;
- aarch64 = !cpsr.width;
+ isSecure = inSecureState(tc) &&
+ !(tranType & HypMode) && !(tranType & S1S2NsTran);
+
+ const OperatingMode op_mode = (OperatingMode) (uint8_t)cpsr.mode;
+ aarch64 = opModeIs64(op_mode) ||
+ (opModeToEL(op_mode) == EL0 && ELIs64(tc, EL1));
+
if (aarch64) { // AArch64
aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el;
switch (aarch64EL) {
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