changeset be6065c1d8d2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=be6065c1d8d2
description:
stats: update and fix e273e86a873d
diffstat:
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
| 62 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
| 62 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
| 126 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 5987 ++++-----
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 116 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
| 64 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
| 98 +-
tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
| 879 +
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
| 1214 ++
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
| 520 +
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
| 1013 +
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
| 515 +
tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
| 803 +
tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
| 921 +
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
| 1238 ++
tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
| 243 +
tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
| 658 +
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
| 1053 +
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
| 127 +
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
| 521 +
tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
| 762 +
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
| 1019 +
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
| 534 +
tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
| 882 +
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
| 1195 +
tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
| 243 +
tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
| 650 +
tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
| 800 +
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
| 1055 +
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
| 152 +
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
| 548 +
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
| 906 +
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
| 1232 ++
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
| 243 +
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
| 659 +
tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
| 799 +
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
| 1057 +
tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
| 916 +
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
| 1218 ++
tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
| 807 +
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
| 1095 +
tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
| 152 +
tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
| 543 +
tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
| 917 +
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
| 1237 ++
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
| 243 +
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
| 655 +
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
| 127 +
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
| 515 +
tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
| 764 +
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
| 1035 +
tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
| 882 +
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
| 1172 +
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
| 1008 +
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
| 64 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
| 64 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 64 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
| 284 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 190 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
| 64 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
| 180 +-
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
| 12 +-
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
| 12 +-
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
| 947 +
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
| 124 +
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
| 474 +
tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
| 243 +
tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
| 648 +
tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
| 124 +
tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
| 127 +
tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
| 152 +
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
| 2902 ++++
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
| 997 +
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
| 1644 ++
tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
| 152 +
tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
| 546 +
tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
| 243 +
tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
| 662 +
tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
| 124 +
tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
| 535 +
tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
| 152 +
tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
| 534 +
tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
| 243 +
tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
| 644 +
tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
| 124 +
tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
| 515 +
tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
| 127 +
tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
| 507 +
88 files changed, 52940 insertions(+), 3726 deletions(-)
diffs (truncated from 59162 to 300 lines):
diff -r e7c9353aa537 -r be6065c1d8d2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
Tue May 31 12:14:40 2016 +0100
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
Tue May 31 16:55:47 2016 +0100
@@ -4,11 +4,11 @@
sim_ticks 2847227406000 #
Number of ticks simulated
final_tick 2847227406000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 172654 #
Simulator instruction rate (inst/s)
-host_op_rate 209070 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3861033235 #
Simulator tick rate (ticks/s)
-host_mem_usage 617124 #
Number of bytes of host memory used
-host_seconds 737.43 #
Real time elapsed on the host
+host_inst_rate 111277 #
Simulator instruction rate (inst/s)
+host_op_rate 134747 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2488466073 #
Simulator tick rate (ticks/s)
+host_mem_usage 617520 #
Number of bytes of host memory used
+host_seconds 1144.17 #
Real time elapsed on the host
sim_insts 127319545 #
Number of instructions simulated
sim_ops 154173476 #
Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 #
Voltage in Volts
@@ -441,9 +441,9 @@
system.cpu0.dtb.walker.walkRequestOrigin::total 75197
# Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 #
ITB inst hits
system.cpu0.dtb.inst_misses 0 #
ITB inst misses
-system.cpu0.dtb.read_hits 17339980 #
DTB read hits
+system.cpu0.dtb.read_hits 17339981 #
DTB read hits
system.cpu0.dtb.read_misses 61941 #
DTB read misses
-system.cpu0.dtb.write_hits 14540399 #
DTB write hits
+system.cpu0.dtb.write_hits 14540400 #
DTB write hits
system.cpu0.dtb.write_misses 6479 #
DTB write misses
system.cpu0.dtb.flush_tlb 66 #
Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
@@ -454,12 +454,12 @@
system.cpu0.dtb.prefetch_faults 1959 #
Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 521 #
Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 17401921 #
DTB read accesses
-system.cpu0.dtb.write_accesses 14546878 #
DTB write accesses
+system.cpu0.dtb.read_accesses 17401922 #
DTB read accesses
+system.cpu0.dtb.write_accesses 14546879 #
DTB write accesses
system.cpu0.dtb.inst_accesses 0 #
ITB inst accesses
-system.cpu0.dtb.hits 31880379 #
DTB hits
+system.cpu0.dtb.hits 31880381 #
DTB hits
system.cpu0.dtb.misses 68420 #
DTB misses
-system.cpu0.dtb.accesses 31948799 #
DTB accesses
+system.cpu0.dtb.accesses 31948801 #
DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0
# Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data
0 # Table walker requests started/completed,
data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst
0 # Table walker requests started/completed,
data/inst
@@ -593,9 +593,9 @@
system.cpu0.idleCycles 38694848 #
Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements 715130 #
number of replacements
system.cpu0.dcache.tags.tagsinuse 500.249385 #
Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 30394668 #
Total number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs 30394670 #
Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 715642 #
Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 42.471890 #
Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 42.471892 #
Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 356009000 #
Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.249385
# Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977050
# Average percentage of cache occupancy
@@ -605,22 +605,22 @@
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316
# Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70
# Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1
# Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 63780149 #
Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 63780149 #
Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 15810331
# number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 15810331 #
number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 13424811
# number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 13424811 #
number of WriteReq hits
+system.cpu0.dcache.tags.tag_accesses 63780153 #
Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 63780153 #
Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 15810332
# number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 15810332 #
number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 13424812
# number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 13424812 #
number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320440
# number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 320440 #
number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365226
# number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 365226
# number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361080
# number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 361080
# number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 29235142 #
number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 29235142 #
number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 29555582
# number of overall hits
-system.cpu0.dcache.overall_hits::total 29555582 #
number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data 29235144 #
number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 29235144 #
number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 29555584
# number of overall hits
+system.cpu0.dcache.overall_hits::total 29555584 #
number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 463723
# number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 463723 #
number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 580901
# number of WriteReq misses
@@ -649,20 +649,20 @@
system.cpu0.dcache.demand_miss_latency::total 16499002500
# number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 16499002500
# number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 16499002500
# number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 16274054
# number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 16274054
# number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 14005712
# number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 14005712
# number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 16274055
# number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 16274055
# number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 14005713
# number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 14005713
# number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456923
# number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 456923
# number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386533
# number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 386533
# number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381647
# number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381647
# number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 30279766
# number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 30279766 #
number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 30736689
# number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 30736689
# number of overall (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data 30279768
# number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 30279768 #
number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 30736691
# number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 30736691
# number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028495
# miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.028495
# miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041476
# miss rate for WriteReq accesses
diff -r e7c9353aa537 -r be6065c1d8d2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
Tue May 31 12:14:40 2016 +0100
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
Tue May 31 16:55:47 2016 +0100
@@ -4,11 +4,11 @@
sim_ticks 2858505242500 #
Number of ticks simulated
final_tick 2858505242500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 171882 #
Simulator instruction rate (inst/s)
-host_op_rate 207819 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4390877747 #
Simulator tick rate (ticks/s)
-host_mem_usage 578076 #
Number of bytes of host memory used
-host_seconds 651.01 #
Real time elapsed on the host
+host_inst_rate 125507 #
Simulator instruction rate (inst/s)
+host_op_rate 151748 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3206183180 #
Simulator tick rate (ticks/s)
+host_mem_usage 578080 #
Number of bytes of host memory used
+host_seconds 891.56 #
Real time elapsed on the host
sim_insts 111897168 #
Number of instructions simulated
sim_ops 135292215 #
Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 #
Voltage in Volts
@@ -403,9 +403,9 @@
system.cpu.dtb.walker.walkRequestOrigin::total 74017
# Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 #
ITB inst hits
system.cpu.dtb.inst_misses 0 #
ITB inst misses
-system.cpu.dtb.read_hits 24710832 #
DTB read hits
+system.cpu.dtb.read_hits 24710833 #
DTB read hits
system.cpu.dtb.read_misses 59358 #
DTB read misses
-system.cpu.dtb.write_hits 19424403 #
DTB write hits
+system.cpu.dtb.write_hits 19424404 #
DTB write hits
system.cpu.dtb.write_misses 6793 #
DTB write misses
system.cpu.dtb.flush_tlb 64 #
Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
@@ -416,12 +416,12 @@
system.cpu.dtb.prefetch_faults 1789 #
Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 754 #
Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 24770190 #
DTB read accesses
-system.cpu.dtb.write_accesses 19431196 #
DTB write accesses
+system.cpu.dtb.read_accesses 24770191 #
DTB read accesses
+system.cpu.dtb.write_accesses 19431197 #
DTB write accesses
system.cpu.dtb.inst_accesses 0 #
ITB inst accesses
-system.cpu.dtb.hits 44135235 #
DTB hits
+system.cpu.dtb.hits 44135237 #
DTB hits
system.cpu.dtb.misses 66151 #
DTB misses
-system.cpu.dtb.accesses 44201386 #
DTB accesses
+system.cpu.dtb.accesses 44201388 #
DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
# Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data
0 # Table walker requests started/completed,
data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst
0 # Table walker requests started/completed,
data/inst
@@ -551,9 +551,9 @@
system.cpu.idleCycles 104690673 #
Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 842468 #
number of replacements
system.cpu.dcache.tags.tagsinuse 511.899803 #
Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 42541757 #
Total number of references to valid blocks.
+system.cpu.dcache.tags.total_refs 42541759 #
Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 842980 #
Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 50.465915 #
Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 50.465917 #
Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 594757500 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.899803
# Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999804
# Average percentage of cache occupancy
@@ -563,22 +563,22 @@
system.cpu.dcache.tags.age_task_id_blocks_1024::1 361
# Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 49
# Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1
# Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 175934547 #
Number of tag accesses
-system.cpu.dcache.tags.data_accesses 175934547 #
Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 23016254 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23016254 #
number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18262412 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18262412 #
number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 175934555 #
Number of tag accesses
+system.cpu.dcache.tags.data_accesses 175934555 #
Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 23016255 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 23016255 #
number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 18262413 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 18262413 #
number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 356302
# number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 356302 #
number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 443705
# number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 443705
# number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460205
# number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460205
# number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 41278666 #
number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 41278666 #
number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 41634968 #
number of overall hits
-system.cpu.dcache.overall_hits::total 41634968 #
number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 41278668 #
number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 41278668 #
number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 41634970 #
number of overall hits
+system.cpu.dcache.overall_hits::total 41634970 #
number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 493842
# number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 493842 #
number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 547981
# number of WriteReq misses
@@ -605,20 +605,20 @@
system.cpu.dcache.demand_miss_latency::total 43652936479
# number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 43652936479
# number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 43652936479
# number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 23510096
# number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 23510096 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 18810393
# number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 18810393
# number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 23510097
# number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 23510097 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 18810394
# number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 18810394
# number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 526172
# number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 526172
# number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466016
# number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 466016
# number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460207
# number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460207
# number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 42320489
# number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 42320489 #
number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 42846661
# number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 42846661 #
number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 42320491
# number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 42320491 #
number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 42846663
# number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 42846663 #
number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021006
# miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021006
# miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029132
# miss rate for WriteReq accesses
diff -r e7c9353aa537 -r be6065c1d8d2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
Tue May 31 12:14:40 2016 +0100
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
Tue May 31 16:55:47 2016 +0100
@@ -4,11 +4,11 @@
sim_ticks 2832862976500 #
Number of ticks simulated
final_tick 2832862976500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 92547 #
Simulator instruction rate (inst/s)
-host_op_rate 112251 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2318051416 #
Simulator tick rate (ticks/s)
+host_inst_rate 63021 #
Simulator instruction rate (inst/s)
+host_op_rate 76439 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1578508192 #
Simulator tick rate (ticks/s)
host_mem_usage 579360 #
Number of bytes of host memory used
-host_seconds 1222.09 #
Real time elapsed on the host
+host_seconds 1794.65 #
Real time elapsed on the host
sim_insts 113100501 #
Number of instructions simulated
sim_ops 137180951 #
Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 #
Voltage in Volts
@@ -395,9 +395,9 @@
system.cpu.checker.dtb.walker.walkRequestOrigin::total 17252
# Table walker requests started/completed, data/inst
system.cpu.checker.dtb.inst_hits 0 #
ITB inst hits
system.cpu.checker.dtb.inst_misses 0 #
ITB inst misses
-system.cpu.checker.dtb.read_hits 24576303 #
DTB read hits
+system.cpu.checker.dtb.read_hits 24576304 #
DTB read hits
system.cpu.checker.dtb.read_misses 8296 #
DTB read misses
-system.cpu.checker.dtb.write_hits 19632669 #
DTB write hits
+system.cpu.checker.dtb.write_hits 19632670 #
DTB write hits
system.cpu.checker.dtb.write_misses 1412 #
DTB write misses
system.cpu.checker.dtb.flush_tlb 128 #
Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 1834 #
Number of times TLB was flushed by MVA
@@ -408,12 +408,12 @@
system.cpu.checker.dtb.prefetch_faults 1622 #
Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 445 #
Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 24584599 #
DTB read accesses
-system.cpu.checker.dtb.write_accesses 19634081 #
DTB write accesses
+system.cpu.checker.dtb.read_accesses 24584600 #
DTB read accesses
+system.cpu.checker.dtb.write_accesses 19634082 #
DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 #
ITB inst accesses
-system.cpu.checker.dtb.hits 44208972 #
DTB hits
+system.cpu.checker.dtb.hits 44208974 #
DTB hits
system.cpu.checker.dtb.misses 9708 #
DTB misses
-system.cpu.checker.dtb.accesses 44218680 #
DTB accesses
+system.cpu.checker.dtb.accesses 44218682 #
DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0
# Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data
0 # Table walker requests started/completed,
data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst
0 # Table walker requests started/completed,
data/inst
@@ -568,9 +568,9 @@
system.cpu.dtb.walker.walkRequestOrigin::total 80086
# Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 #
ITB inst hits
system.cpu.dtb.inst_misses 0 #
ITB inst misses
-system.cpu.dtb.read_hits 25410889 #
DTB read hits
+system.cpu.dtb.read_hits 25410890 #
DTB read hits
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