> On Juni 15, 2016, 2:23 nachm., Andreas Sandberg wrote: > > util/tlm/tlm_elastic.py, line 126 > > <http://reviews.gem5.org/r/3477/diff/2/?file=55598#file55598line126> > > > > This shouldn't be needed since you're not in FS mode (and you're > > simulating a trace CPU). > > Matthias Jung wrote: > Actually cpu.createInterruptController() is needed it wont work else :/
fatal condition interrupts.size() != numThreads occurred: CPU system.cpu has 0 interrupt controllers, but is expecting one per thread (1) - Matthias ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3477/#review8408 ----------------------------------------------------------- On Juni 14, 2016, 9:06 nachm., Matthias Jung wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3477/ > ----------------------------------------------------------- > > (Updated Juni 14, 2016, 9:06 nachm.) > > > Review request for Default and Andreas Sandberg. > > > Repository: gem5 > > > Description > ------- > > This patch adds an example configuration for elastic trace playing into the > SystemC world, similar to the already existing traffic generator example in > /util/tlm. > > > Diffs > ----- > > util/tlm/README fc247b9c42b6 > util/tlm/tlm_elastic.py PRE-CREATION > > Diff: http://reviews.gem5.org/r/3477/diff/ > > > Testing > ------- > > > Thanks, > > Matthias Jung > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
