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Thanks for contributing this. Could you please change the commit message such that the summary (first line) is no more than 65 characters and the body no more than 75 characters. The commit summary should start with the mem keyword. src/mem/cache/tags/base_set_assoc.hh (line 217) <http://reviews.gem5.org/r/3502/#comment7316> Would it make sense to move most of this code in the constructor? The flag sequentialAccess and the condition lookupLatency >= dataLantency shouldn't change during the simulation. src/mem/cache/tags/fa_lru.cc (line 212) <http://reviews.gem5.org/r/3502/#comment7315> Same here - Nikos Nikoleris On June 20, 2016, 3:07 p.m., Sophiane SENNI wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3502/ > ----------------------------------------------------------- > > (Updated June 20, 2016, 3:07 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11536:1a3a96d435ed > --------------------------- > cache: Split the hit latency into tag lookup latency and data access latency > > If the cache access mode is parallel ("sequential_access" parameter set to > "False"), tags and data are accessed in parallel. Therefore, the hit latency > is the maximum latency between tag lookup latency and data access latency. On > the other hand, if the cache access mode is sequential ("sequential_access" > parameter set to "True"), tags and data are accessed sequentially. Therefore, > the hit latency is the sum of tag lookup latency plus data access latency. > > > Diffs > ----- > > configs/common/Caches.py 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/Cache.py 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/base.hh 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/base.cc 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/tags/Tags.py 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/tags/base.hh 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/tags/base.cc 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/tags/base_set_assoc.hh > 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/tags/fa_lru.hh 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/tags/fa_lru.cc 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > > Diff: http://reviews.gem5.org/r/3502/diff/ > > > Testing > ------- > > Tested using --Debug-flags=Cache > > > Thanks, > > Sophiane SENNI > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
