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(Updated juin 28, 2016, 1:06 après-midi) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 11536:1a3a96d435ed --------------------------- mem: Split the hit_latency into tag_latency and data_latency If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Diffs (updated) ----- configs/common/Caches.py 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 src/mem/cache/Cache.py 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 src/mem/cache/base.hh 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 src/mem/cache/tags/fa_lru.cc 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 src/mem/cache/tags/fa_lru.hh 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 src/mem/cache/tags/base_set_assoc.hh 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 src/mem/cache/tags/base.cc 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 src/mem/cache/tags/base.hh 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 src/mem/cache/tags/Tags.py 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 src/mem/cache/base.cc 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 Diff: http://reviews.gem5.org/r/3502/diff/ Testing ------- Tested using --Debug-flags=Cache Thanks, Sophiane SENNI _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
