changeset cc3252906757 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cc3252906757
description:
arm: invalidate TLB miscreg cache on modification of HSCTLR
Change-Id: I5212c91c56435fe008950ed99feacc6921609226
diffstat:
src/arch/arm/isa.cc | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diffs (18 lines):
diff -r 9eac6e12c673 -r cc3252906757 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Tue Aug 02 10:38:01 2016 +0100
+++ b/src/arch/arm/isa.cc Tue Aug 02 10:38:01 2016 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2015 ARM Limited
+ * Copyright (c) 2010-2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1629,6 +1629,7 @@
case MISCREG_TCR_EL3:
case MISCREG_SCTLR_EL2:
case MISCREG_SCTLR_EL3:
+ case MISCREG_HSCTLR:
case MISCREG_TTBR0_EL1:
case MISCREG_TTBR1_EL1:
case MISCREG_TTBR0_EL2:
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