changeset 868c31fcca24 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=868c31fcca24
description:
arm: enable EL2 support
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
diffstat:
src/arch/arm/ArmISA.py | 5 ++---
src/arch/arm/faults.cc | 20 +++++++++-----------
src/arch/arm/isa.cc | 11 ++++-------
src/arch/arm/isa.hh | 7 +++----
src/arch/arm/miscregs.cc | 12 +++++-------
src/arch/arm/system.hh | 7 +++----
src/arch/arm/table_walker.cc | 15 +++++++--------
src/arch/arm/utility.cc | 44 +++++++++++++++++++++-----------------------
8 files changed, 54 insertions(+), 67 deletions(-)
diffs (277 lines):
diff -r cc3252906757 -r 868c31fcca24 src/arch/arm/ArmISA.py
--- a/src/arch/arm/ArmISA.py Tue Aug 02 10:38:01 2016 +0100
+++ b/src/arch/arm/ArmISA.py Tue Aug 02 10:38:01 2016 +0100
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013, 2015 ARM Limited
+# Copyright (c) 2012-2013, 2015-2016 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -117,8 +117,7 @@
"AArch64 Memory Model Feature Register 1")
# !GICv3 CP15 | AdvSIMD | FP | !EL3 | !EL2 | EL1 (AArch64) | EL0 (AArch64)
- # (no AArch32/64 interprocessing support for now)
- id_aa64pfr0_el1 = Param.UInt64(0x0000000000000011,
+ id_aa64pfr0_el1 = Param.UInt64(0x0000000000000022,
"AArch64 Processor Feature Register 0")
# Reserved for future expansion
id_aa64pfr1_el1 = Param.UInt64(0x0000000000000000,
diff -r cc3252906757 -r 868c31fcca24 src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc Tue Aug 02 10:38:01 2016 +0100
+++ b/src/arch/arm/faults.cc Tue Aug 02 10:38:01 2016 +0100
@@ -338,11 +338,10 @@
assert(ArmSystem::haveSecurity(tc));
vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
break;
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // assert(ArmSystem::haveVirtualization(tc));
- // vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
- // break;
+ case EL2:
+ assert(ArmSystem::haveVirtualization(tc));
+ vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
+ break;
case EL1:
vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
break;
@@ -596,12 +595,11 @@
elr_idx = MISCREG_ELR_EL1;
spsr_idx = MISCREG_SPSR_EL1;
break;
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // assert(ArmSystem::haveVirtualization());
- // elr_idx = MISCREG_ELR_EL2;
- // spsr_idx = MISCREG_SPSR_EL2;
- // break;
+ case EL2:
+ assert(ArmSystem::haveVirtualization(tc));
+ elr_idx = MISCREG_ELR_EL2;
+ spsr_idx = MISCREG_SPSR_EL2;
+ break;
case EL3:
assert(ArmSystem::haveSecurity(tc));
elr_idx = MISCREG_ELR_EL3;
diff -r cc3252906757 -r 868c31fcca24 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Tue Aug 02 10:38:01 2016 +0100
+++ b/src/arch/arm/isa.cc Tue Aug 02 10:38:01 2016 +0100
@@ -359,9 +359,8 @@
if (haveSecurity) {
miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870;
miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
- // @todo: uncomment this to enable Virtualization
- // } else if (haveVirtualization) {
- // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
+ } else if (haveVirtualization) {
+ miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
} else {
miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870;
// Always non-secure
@@ -391,15 +390,13 @@
// Enforce consistency with system-level settings...
// EL3
- // (no AArch32/64 interprocessing support for now)
miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
- haveSecurity ? 0x1 : 0x0);
+ haveSecurity ? 0x2 : 0x0);
// EL2
- // (no AArch32/64 interprocessing support for now)
miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
- haveVirtualization ? 0x1 : 0x0);
+ haveVirtualization ? 0x2 : 0x0);
// Large ASID support
miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
diff -r cc3252906757 -r 868c31fcca24 src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh Tue Aug 02 10:38:01 2016 +0100
+++ b/src/arch/arm/isa.hh Tue Aug 02 10:38:01 2016 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2015 ARM Limited
+ * Copyright (c) 2010, 2012-2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -261,9 +261,8 @@
switch (el) {
case EL3:
return INTREG_SP3;
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // return INTREG_SP2;
+ case EL2:
+ return INTREG_SP2;
case EL1:
return INTREG_SP1;
case EL0:
diff -r cc3252906757 -r 868c31fcca24 src/arch/arm/miscregs.cc
--- a/src/arch/arm/miscregs.cc Tue Aug 02 10:38:01 2016 +0100
+++ b/src/arch/arm/miscregs.cc Tue Aug 02 10:38:01 2016 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, 2015 ARM Limited
+ * Copyright (c) 2010-2013, 2015-2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -2118,9 +2118,8 @@
case EL1:
return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
miscRegInfo[reg][MISCREG_PRI_NS_RD];
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // return miscRegInfo[reg][MISCREG_HYP_RD];
+ case EL2:
+ return miscRegInfo[reg][MISCREG_HYP_RD];
case EL3:
return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
miscRegInfo[reg][MISCREG_MON_NS1_RD];
@@ -2163,9 +2162,8 @@
case EL1:
return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
miscRegInfo[reg][MISCREG_PRI_NS_WR];
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // return miscRegInfo[reg][MISCREG_HYP_WR];
+ case EL2:
+ return miscRegInfo[reg][MISCREG_HYP_WR];
case EL3:
return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
miscRegInfo[reg][MISCREG_MON_NS1_WR];
diff -r cc3252906757 -r 868c31fcca24 src/arch/arm/system.hh
--- a/src/arch/arm/system.hh Tue Aug 02 10:38:01 2016 +0100
+++ b/src/arch/arm/system.hh Tue Aug 02 10:38:01 2016 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013, 2015 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015-2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -184,9 +184,8 @@
{
if (_haveSecurity)
return EL3;
- // @todo: uncomment this to enable Virtualization
- // if (_haveVirtualization)
- // return EL2;
+ if (_haveVirtualization)
+ return EL2;
return EL1;
}
diff -r cc3252906757 -r 868c31fcca24 src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc Tue Aug 02 10:38:01 2016 +0100
+++ b/src/arch/arm/table_walker.cc Tue Aug 02 10:38:01 2016 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2015 ARM Limited
+ * Copyright (c) 2010, 2012-2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -223,7 +223,7 @@
// ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672
// aarch32/translation/translation/AArch32.TranslateAddress dictates
// even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64.
- currState->aarch64 = opModeIs64(currOpMode(_tc)) ||
+ currState->aarch64 = isStage2 || opModeIs64(currOpMode(_tc)) ||
((currEL(_tc) == EL0) && ELIs64(_tc, EL1));
currState->el = currEL(_tc);
currState->transState = _trans;
@@ -255,12 +255,11 @@
currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1);
break;
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // assert(haveVirtualization);
- // currState->sctlr =
currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
- // currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2);
- // break;
+ case EL2:
+ assert(_haveVirtualization);
+ currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
+ currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2);
+ break;
case EL3:
assert(haveSecurity);
currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3);
diff -r cc3252906757 -r 868c31fcca24 src/arch/arm/utility.cc
--- a/src/arch/arm/utility.cc Tue Aug 02 10:38:01 2016 +0100
+++ b/src/arch/arm/utility.cc Tue Aug 02 10:38:01 2016 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2009-2014 ARM Limited
+ * Copyright (c) 2009-2014, 2016 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -235,14 +235,14 @@
return opModeIs64(currOpMode(tc));
case EL1:
{
- // @todo: uncomment this to enable Virtualization
- // if (ArmSystem::haveVirtualization(tc)) {
- // HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
- // return hcr.rw;
- // }
- assert(ArmSystem::haveSecurity(tc));
- SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
- return scr.rw;
+ if (ArmSystem::haveVirtualization(tc)) {
+ HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+ return hcr.rw;
+ } else if (ArmSystem::haveSecurity(tc)) {
+ SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+ return scr.rw;
+ }
+ panic("must haveSecurity(tc)");
}
case EL2:
{
@@ -286,13 +286,12 @@
else if (!bits(addr, 55, 48) && tcr.tbi0)
return bits(addr,55, 0);
break;
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // assert(ArmSystem::haveVirtualization());
- // tcr = tc->readMiscReg(MISCREG_TCR_EL2);
- // if (tcr.tbi)
- // return addr & mask(56);
- // break;
+ case EL2:
+ assert(ArmSystem::haveVirtualization(tc));
+ tcr = tc->readMiscReg(MISCREG_TCR_EL2);
+ if (tcr.tbi)
+ return addr & mask(56);
+ break;
case EL3:
assert(ArmSystem::haveSecurity(tc));
if (tcr.tbi)
@@ -320,13 +319,12 @@
else if (!bits(addr, 55, 48) && tcr.tbi0)
return bits(addr,55, 0);
break;
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // assert(ArmSystem::haveVirtualization());
- // tcr = tc->readMiscReg(MISCREG_TCR_EL2);
- // if (tcr.tbi)
- // return addr & mask(56);
- // break;
+ case EL2:
+ assert(ArmSystem::haveVirtualization(tc));
+ tcr = tc->readMiscReg(MISCREG_TCR_EL2);
+ if (tcr.tbi)
+ return addr & mask(56);
+ break;
case EL3:
assert(ArmSystem::haveSecurity(tc));
tcr = tc->readMiscReg(MISCREG_TCR_EL3);
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